UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 399

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Non-
maskable
Maskable
Interrupt
Type of
Notes 1. The default priority is the priority order when two or more maskable interrupt requests are generated
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 19-1.
3.
Priority
simultaneously. 0 is the highest and 23 is the lowest.
Default
PD780078Y Subseries only.
10
11
12
13
14
15
16
17
18
—
0
1
2
3
4
5
6
7
8
9
Note 1
INTWDT
INTWDT
INTP0
INTP1
INTP2
INTP3
INTSER0
INTSR0
INTST0
INTCSI1
INTCSI3
INTIIC0
INTWTI
INTTM000
INTTM010
INTTM50
INTTM51
INTAD0
INTWT
INTKR
Name
Note 3
Table 19-1. Interrupt Source List (1/2)
Watchdog timer overflow (non-maskable
interrupt selected)
Watchdog timer overflow (interval timer
selected)
Pin input edge detection
Generation of UART0 reception error
End of UART0 reception
End of UART0 transmission
End of CSI1 communication
End of SIO3 communication
End of IIC0 communication
Reference time interval signal from watch timer
Match of TM00 and CR000
(when compare register is specified)
Detection of valid edge of TI010
(when capture register is specified)
Match of TM00 and CR010
(when compare register is specified)
Detection of valid edge of TI000
(when capture register is specified)
Match of TM50 and CR50
Match of TM51 and CR51
End of conversion by A/D converter
Watch timer overflow
Falling edge detection of port 4
CHAPTER 19 INTERRUPT FUNCTIONS
Interrupt Source
User’s Manual U14260EJ4V0UD
Trigger
Internal/
External
External
External
Internal
Internal
Vector Table
0006H
0008H
000AH
000CH
0010H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0026H
0004H
000EH
0012H
0024H
0028H
Address
Configuration
Type
Basic
(B)
(C)
(D)
(A)
(B)
Note 2
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