UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 265

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(When framing/overrun error occurs)
(e) Receive errors
Three types of errors can occur during a receive operation: a parity error, framing error, or overrun error.
If, as the result of data reception, an error flag is set in asynchronous serial interface status register 0 (ASIS0),
a receive error interrupt request (INTSER0) will occur. Receive error interrupts are generated before the
receive completion interrupt request (INTSR0). Table 14-4 lists the causes behind receive errors.
As part of receive error interrupt request (INTSER0) servicing, the contents of ASIS0 can be read to determine
which type of error occurred during the receive operation (see Table 14-4 and Figure 14-12).
The contents of ASIS0 are reset (to 0) when receive buffer register 0 (RXB0) is read or when the next data
is received (if the next data contains an error, its error flag will be set).
(When parity error occurs)
Note Even if a receive error occurs when the ISRM0 bit has been set (1), INTSR0 does not occur.
Cautions 1. The contents of asynchronous serial interface status register 0 (ASIS0) are reset (to
Parity error
Framing error
Overrun error
Receive Error
2. Be sure to read the contents of receive buffer register 0 (RXB0) after the receive
RxD0 (input)
INTSR0
INTSER0
INTSER0
0) when receive buffer register 0 (RXB0) is read or when the next data is received. To
obtain information about the error, be sure to read the contents of ASIS0 before reading
RXB0.
completion interrupt request has occurred even when a receive error has occurred. If
RXB0 is not read after the receive completion interrupt request has occurred, overrun
errors will occur during the next data receive operations and the receive error status
will remain until the contents of RXB0 are read.
Parity specified does not match parity of receive data
Stop bit was not detected
Reception of the next data was completed before data was read from receive buffer
register 0 (RXB0)
Note
CHAPTER 14 SERIAL INTERFACE UART0
Table 14-4. Causes of Receive Errors
Figure 14-12. Receive Error Timing
Start
User’s Manual U14260EJ4V0UD
D0
D1
Cause
D2
D6
D7
Parity
Stop
263