H27UAG8T2ATR-BC HYNIX SEMICONDUCTOR, H27UAG8T2ATR-BC Datasheet
H27UAG8T2ATR-BC
Specifications of H27UAG8T2ATR-BC
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H27UAG8T2ATR-BC Summary of contents
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NAND Flash Rev 1.0 /Aug. 2010 16Gb (2048M x 8bit) NAND Flash H27UAG8T2B Release H27UAG8T2B Series 1 ...
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Document Title 16Gbit (2048 bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 0.1 Draft version Release 1.0 Final version Release Spec. change : tWHR ( before : 80ns min / after : 100ns min) ...
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Multilevel Cell technology ■ Supply Voltage - 3.3V device : Vcc = 2 3.6 V Vcc = 2 3.6 V ■ Organization - Page size : 8,640 Bytes(8,192+448 bytes) - Block size : 256 pages(2M+112K ...
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SUMMARY DESCRIPTION The H27UAG8T2B is a single 3.3V 16Gbit NAND flash memory. The Device contains 2 planes in a single die. Each plane is made up of the 512 blocks. Each block consists of 256 programmable pages. Each page ...
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Packaging Information Figure 1. 48-TSOP1 Contact, x8 Device ■ Figure 1-1. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline ■ Symbol Rev 1.0 / Aug. 2010 16Gb ...
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Symbol alpha 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Mechanical Data Pin Diagram Figure 2. Pin Diagram ■ CE# WE# RE# ALE CLE WP# Pin Names Rev 1.0 / Aug. 2010 16Gb (2048M ...
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I/O7~I/O0 CLE ALE CE# RE# R/B# WE# WP# VCC VSS NC 1.3. PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O0-I/ The I/O pins are used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out cycles during O7 read / write ...
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Notes: A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during ...
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Array Organization Figure 4. Array organization ■ 8,640 bytes 8,192 8,192 1 Block Plane 0 1.6. Addressing Bus cycle I/O0 I/ Cycle Cycle rd A14 A15 3 Cycle th A22 A23 ...
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Command Set FUNCTION PAGE READ READ FOR COPY-BACK 1) RANDOM DATA OUTPUT 5) SINGLE/multi plane CACHE READ SINGLE/multi plane CACHE READ 5) END READ ID READ STATUS REGISTER PAGE PGM (start) / CACHE PGM 5) (end) 1) RANDOM DATA ...
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Caution: 1. Any undefined command inputs are prohibited except for above command set. 2. Multi Plane page read, Multi Plane cache read, and Multi Plane read for copy-back must be used after Multi Plane programmed page, Multi Plane cache program, ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because ...
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Bad Block Replacement This device may have the invalid blocks when shipped from factory. An invalid block is one that contains one or more bad bits. Over the lifetime of the device additional Bad Blocks may develop. In this ...
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Electrical Characteristics 2.1. Valid Blocks Symbol Valid Block N VB Number Notes: 1. The 1st block is guaranteed valid block at the time of shipment. 2. This single device has a maximum of 25 invalid blocks. ...
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DC and Operating Characteristics Parameter Power on reset current Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output ...
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Pin Capacitance (T =25°C, F=1.0㎒) A Symbol Parameter C Input Capacitance IN C Input/Output Capacitance I/O 2.6. Program/ Read / Erase Characteristics Parameter Program (following 10h) Cache Program (following 15h) multi plane Program / multi plane Cache Program / ...
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AC Timing Characteristics Parameter CLE setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time WE# high hold time Data ...
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Device resetting time (Read/Program/Erase) Write protection time Notes Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. Program / Erase Enable Operation: WP# high to WE# High. Program / Erase ...
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Device Identifier Coding Parameter Device Identifier Byte 2.10. Read ID Data Table Bus Part Number Voltage Width H27UAG8T2B 3. 2.10.1. 3 Byte of Device Identifier ...
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Byte of Device Identifier Description th Description 4 cycle 2KB Page Size 4KB (Without Spare Area) 8KB Reserved 128KB 256KB 512KB Block Size 768KB (Without Spare area) 1MB 2MB Reserved Reserved 128B 224B 448B Reserved Redundant Area ...
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Byte of Device Identifier Description th Description 6 cycle 48nm 41nm 32nm Reserved NAND Technology Reserved Reserved Reserved Reserved Not Support EDO Support Support SDR NAND Interface DDR Reserved Rev 1.0 / Aug. 2010 H27UAG8T2B Series 16Gb ...
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Timing Diagram Bus Operation There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. 3.1. Command Latch Cycle Timings Figure 6. Command latch timings ■ ...
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Address Latch Cycle Timings Figure 7. Address latch timings ■ tCLS CLE tCS tWC CE tWP WE tALS tALH ALE tDH tDS I/Ox Col.Add1 3.3. Input Data Latch Cycle Timings ■ Figure 8. Input data cycle timings CLE CE# ...
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Note: Data Input cycle is accepted to data register on the rising edge of WE#, when CLE and CE# and ALE are low, and device is not Busy state. 3.4. Data Output Cycle Timings (CLE=L, WE#=H, ALE=L, WP#=H) Figure 9. ...
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RLOH t starts to be valid when frequency is lower than 33MHz. RHOH 3.6. Read Status Cycle Timings Figure 11. Read status timings ■ CLS CLE t CS ...
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Page Read Operation Timings (Read One Page) Figure 13. Page read operation timings ■ CE# CLE t ALE WC WE# RE# Col. Col. Row. I/Ox 00h Add1 Add2 Add1 R/B# 3.9. Page Read Operation Timings (Intercepted by CE#) Figure ...
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Page Read Operation Timings with CE# don't care Figure 15. Page read operation timings with CE# don't care ■ Note: Random data output is available within a page. 3.11. Random Data Output Timings Figure 16. Random data output timings ...
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Multi Plane Page Read Operation with Random Data output Timings Figure 17. Multi plane page read operation timings with random data output ■ Notes: 1. Multi Plane Page addresses are required to be the same. 2. Multi Plane Random ...
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Cache Read Operation Timings ■ Figure 18. Cache read operation timings Notes: 1. The column address will be reset the 31h/3Fh command input. 2. Cache read operation is available only within a block. Rev 1.0 / ...
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Multi Plane Cache Read Operation Timings Figure 19. Multi plane cache read operation Timings ■ Notes: 1. The column address will be reset the 31h/3Fh command input. 2. Cache read operation is available only within a ...
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Read ID Operation Timings ■ Figure 20. Read ID operation timings CE# CLE WE# t WHR ALE RE# 90h 00h I/Ox 3.16. Page Program Operation Timings Figure 21. Page program operation timings ■ Note the time from ...
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Page Program Operation Timings with CE# don't care Figure 22. Page program operation timings with CE# don't care ■ CE# CLE ALE WE# Col. Col. I/Ox 80h Add1 Add1 Note the time from the WE# rising edge ...
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Multi Plane Page Program Operation Timings Figure 25. Multi plane page program operation timing ■ CE# CLE t WC ALE WE# I/Ox Col. 80h Add1 Add2 R/ A13 : Valid A14 ~ A21 Valid (Page M) A22 ...
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Copy-Back Program Operation Timings with Random Date Input Figure 26. Copyback program operation timing with random data input ■ Notes: 1. Copy back operation is allowed only within the same memory plane. 3.21. Cache Program Operation Timings Figure 27. ...
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Multi Plane Cache Program Operation Timings ■ Figure 28. Multi plane cache program operation timings CE# CLE t WC ALE WE# t ADL Col. Col. Row Row Row I/Ox 80h Add1 Add2 Add1 Add2 Add3 R/ A13 ...
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Block Erase Operation Timings Figure 29. Block erase operation timings ■ 3.24. Multi Plane Erase Operation Timings Figure 30. Multi plane erase operation timings ■ CE# CLE ALE t WC WE# RE# Row Row I/Ox 60h Add1 Add2 R/B# ...
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Reset Timings Figure 31. Reset timings ■ CE# CLE WE# I/Ox R/B# Rev 1.0 / Aug. 2010 H27UAG8T2B Series 16Gb (2048M x 8bit) NAND Flash t WB FFh t RST Release 37 ...
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DEVICE OPERATION 4.1. Page Read This operation is initialized by 00h-30h to the command register along with followed by five address input cycles. The 8,640 bytes of data within the selected page are transferred to the data registers in ...
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Cache Read (available only within a block) To improve page read throughput, cache read operation is used within a block. First step is same as normal page read, issuing a page read sequence (00-30h). After random access (R/B# returns ...
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Figure 35. Multi plane page read ■ Page address : Page M Plane address : Fixed “Low” Block address : Block J Address 60h 60h I/Ox (3 Cycle) R/B# Column address : Fixed “Low Page address : Page M Plane ...
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Notes: 1. Plane 0 and plane 1 should be selected within the same chip 2. Only one block should be selected from the each Plane. 3. Multi Plane cache read is available only within a block per plane. 4. Selected ...
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Figure 39. Multi plane read status ■ CLE ALE WE# RE# 78h I/Ox Rev 1.0 / Aug. 2010 16Gb (2048M x 8bit) NAND Flash Row.Add1 Row.Add2 Row.Add3 Release H27UAG8T2B Series Status 42 ...
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Page Program The device is programmed as a page unit. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 times. The program addressing should be done in ...
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Multi Plane Program Device supports multiple plane program possible to program in parallel 2 pages, one per each plane. A multiple plane program cycle consists of a double serial data loading period in which up to 17,280bytes ...
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In addition, the status bit (I/O 5) can be used to determine when the cell programming of the current data register contents is complete. Pass/fail status of only the previous page (I available upon ...
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Multi Plane Cache Program (available only within a block) The device supports multi plane cache program, which enables high program throughput by programming two pages. The serial data-loading period begins by inputting the Serial Data Input command (80h), followed ...
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Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the ...
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Figure 46. Multi plane Copyback program Page address : Page M Plane address : Fixed “Low” Block address : Block J Address 60h 60h I/Ox (3 Cycle) R/B# Column address : Fixed “Low Page address : Page M Plane ...
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Figure 47. Multi plane Copyback program Page address : Page M Plane address : Fixed “Low” Block address : Block J Address I/Ox 60h (3 Cycle) R/B# Column address : Fixed “Low” Page address : Page M Plane address ...
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R/B# output, or the Status bit (I the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When ...
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Figure 50. Reset I/Ox R/B# Rev 1.0 / Aug. 2010 16Gb (2048M x 8bit) NAND Flash FFh t RST Release H27UAG8T2B Series 51 ...
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INTERLEAVED OPERATION Interleaving operations improve the system throughput compared to non-interleaving operations. In the stacked device sharing a common CE# pin, interleaved operation is available. When both chip are ready state, input a com- mand to the chip #1. ...
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Figure 52. Interleaved multi plane page read Address Address Address 60h 30h 60h 60h I/Ox (3cycle) (5cycle) (3cycle) Chip 1 Chip 1 Chip 2 R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) A I/Ox Address Address Data ...
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Figure 54. Interleaved multi plane page program Address. I/Ox 80h 11h Data Input (5cycle) Chip 1 R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) A I/Ox Row. Row. Row. 78h Status Add.1 Add.2 Add.3 Chip 1 R/B# ...
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Interleaved Multi Plane Block Erase Figure 56 shows how to perform two types of interleaved Multi Plane Block Erase operations. This operation must meet two-plane addressing requirements. ■ Figure 56. Interleaved multi plane block erase Address Address 60h 60h ...
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OTHER FEATURES 6.1. Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever V protection and is recommended to be kept at ...
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Figure 58. Ready / Busy ■ Vcc R/B# open drain output GND Device Rp value guidence Vcc (Max (min where IL is the sum of the input current of all devices tied to ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP# goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 59 ~ 62). WE I/Ox 80h WP# R/B# Figure ...
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Application Notes and Comments 7.1. Paired Page Address Information Paired page address ...
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When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also a coupled row paired page data may be damaged. For example, during ...
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Figure 63. Restriction read status in multi plane operation I/O6 => I/O5 => I/O1 => I/O0 => I/Ox Address Data 11h 80h R/B# 7.6. Page Program Failure If the Page Program operation for page address N is fail, remain ...