H27UAG8T2ATR-BC HYNIX SEMICONDUCTOR, H27UAG8T2ATR-BC Datasheet - Page 40

• Manufacturer Part Number: H27UAG8T2ATR-BC
• Description: 58T1891
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27UAG8T2ATR-BC

• Memory Type: Flash - NAND
• Memory Size: 16Gbit
• Memory Configuration: 2048M X 8
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes

Rev 1.0 / Aug. 2010
4.4. Multi Plane Cache Read (available only within a block)
The device supports multi plane cache read, which enables high read throughput by reading two pages in
parallel. Figure 36 shows the command sequence for the multi plane cache read operation. Both confirm commands,
30h and 33h, are valid for the first page read sequence.
■
■
Figure 35. Multi plane page read
Figure 36. Multi plane cache read
R/B#
R/B#
R/B#
I/Ox
I/Ox
I/Ox
R/B#
I/Ox
R/B#
R/B#
I/Ox
I/Ox
A
B
A
B
00h
00h
60h
31h
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
00h
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘Low’
Block address : Block J
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘High’
Block address : Block K
60h
Address
(5 Cycle)
Address
(5 Cycle)
Address
(3 Cycle)
t
Column address : Fixed
Page address : Page M
Plane address : Fixed
Block address : Block K
CBSYR
(5 Cycle)
Address
(3 Cycle)
00h
Address
60h
05h
05h
Column address : Fixed
Page address : Page M
Plane address : Fixed
Block address : Block J
HIGH
LOW
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
05h
(5 Cycle)
Address
Address
(3 Cycle)
Column address : Valid
Address
(2 Cycle)
Column address : Valid
Address
(2 Cycle)
60h
Column address : Valid
(2 Cycle)
LOW
Address
LOW
30h
05h
(3 Cycle)
Address
E0h
E0h
Column address : Valid
16Gb (2048M x 8bit) NAND Flash
(2 Cycle)
Address
Eoh
33h
t
R
Data output
E0h
Data output
Data output
H27UAG8T2B Series
t
R
Data output
Release
A
B
B
A
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