PSB2163T-V31TR Infineon Technologies, PSB2163T-V31TR Datasheet - Page 72
PSB2163T-V31TR
Manufacturer Part Number
PSB2163T-V31TR
Description
IC AUDIO RINGING CODEC 28-PDSO
Manufacturer
Infineon Technologies
Series
ARCOFI®r
Datasheet
1.PSB2163T-V31TR.pdf
(279 pages)
Specifications of PSB2163T-V31TR
Function
CODEC Filter
Interface
IOM-2, PCI, Serial
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
900µA
Power (watts)
1mW
Operating Temperature
-25°C ~ 80°C
Mounting Type
Surface Mount
Package / Case
DSO-28
Includes
Activation and Deactivation, B-Channel and D-Channel HDLC Controllers, D-Channel Priority Handler, Monitor Channel Handler
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
PSB2163T-V31INTR
PSB2163T-V31TR
PSB2163T-V31TR
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Functional Description
2.3.4
Serial Data Interface
If the serial control interface is selected, the ARCOFI supports an additional serial data
interface for B-channel transfer. This control interface consists of five lines: FSC, DCLK,
DX, DR and MCLK.
FSC is a 8-kHz frame synchronization signal.
The DCLK is the clock signal to synchronize the data transfer on both data lines DX and
DR. The rising edge indicates the start of the bit while the falling edge is used to latch
the contents of the received data line DR. If the double clock rate is chosen (twice of the
transmission rate) the first rising edge indicates the start of a bit while the second falling
edge is used to latch the content of the data line.
The data rate of the interface can vary from 64 kbit/s to 4.096 Mbit/s. A frame may
consist of up to 64 time-slots of 8 bits each. The last 6 bits of TSCR (Time Slot
Configuration Register) indicate the selected time-slot from 0 to 63. If a 16-bit mode
(linear mode) is chosen, the lowest data rate is 128 kbit/s and the time-slot must be set
to an even number.
The pin AD/MCLK is a system clock synchronized with FSC (necessary to synchronize
internal PLL).
Figure 33 shows the timing of a serial data interface (256 kbit/s with single clock rate).
Figure 33
Serial Data Interface Timing
Semiconductor Group
71
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