PSB2163T-V31TR Infineon Technologies, PSB2163T-V31TR Datasheet - Page 97
PSB2163T-V31TR
Manufacturer Part Number
PSB2163T-V31TR
Description
IC AUDIO RINGING CODEC 28-PDSO
Manufacturer
Infineon Technologies
Series
ARCOFI®r
Datasheet
1.PSB2163T-V31TR.pdf
(279 pages)
Specifications of PSB2163T-V31TR
Function
CODEC Filter
Interface
IOM-2, PCI, Serial
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
900µA
Power (watts)
1mW
Operating Temperature
-25°C ~ 80°C
Mounting Type
Surface Mount
Package / Case
DSO-28
Includes
Activation and Deactivation, B-Channel and D-Channel HDLC Controllers, D-Channel Priority Handler, Monitor Channel Handler
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
PSB2163T-V31INTR
PSB2163T-V31TR
PSB2163T-V31TR
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GCR
4.2
Value after reset: 00 H
SP
AGCX
AGCR
EVX
SLOT
PU
CAM
LAW
Semiconductor Group
General Configuration Register (GCR)
7
SP
Speakerphone
0: speakerphone support disabled
1: speakerphone support enabled
Automatic Gain Control Transmit
0: automatic gain control disabled
1: automatic gain control enabled; only if speakerphone support
Automatic Gain Control Receive
0: automatic gain control disabled
1: automatic gain control enabled; only if speakerphone support
Enable Voice Transmit
0: disable transmit voice data
1: enable transmit voice data (if GCR.PU = 0, idle code is transmitted)
IOM-2 Slot Select (IOM-2 TE-mode only)
0: bearer channels in IOM-channel 0
1: bearer channels in IOM-channel 1
Power-Up
0: the ARCOFI is placed in standby mode (power-down); all registers
1: the ARCOFI is in a normal operating mode (power-up)
This bit can be directly accessed by the XOP_0/XOP_1 operations.
Chip Address Mode (IOM-2 mode only)
0: two ARCOFIs are connected to the IOM-2 bus
1: only one ARCOFI is connected to the IOM-2 bus
Coding Law
0: A-Law enabled
1: -Law enabled
is enabled (SP = 1)
is enabled (SP = 1)
and coefficient RAM contents are saved and all interface functions
are available
AGCX
AGCR
EVX
96
SLOT
PU
Register Description
CAM
LAW
0
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