PSB2163T-V31TR Infineon Technologies, PSB2163T-V31TR Datasheet - Page 85

• Manufacturer Part Number: PSB2163T-V31TR
• Description: IC AUDIO RINGING CODEC 28-PDSO
• Manufacturer: Infineon Technologies
• Series: ARCOFI®r

Specifications of PSB2163T-V31TR

• Function: CODEC Filter
• Interface: IOM-2, PCI, Serial
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 900µA
• Power (watts): 1mW
• Operating Temperature: -25°C ~ 80°C
• Mounting Type: Surface Mount
• Package / Case: DSO-28
• Includes: Activation and Deactivation, B-Channel and D-Channel HDLC Controllers, D-Channel Priority Handler, Monitor Channel Handler
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2163T-V31INTR; PSB2163T-V31TR

Monitor transfer protocol rules:
Semiconductor Group
A pair of MX and MR in the inactive state for two or more consecutive frames
indicates an idle state or an end of transmission (EOM).
A command stream initiated by a transmitter in the MON-slot is accompanied by an
activated downstream MX-bit.
The receiver acknowledges a received byte by toggling the upstream MR-bit from
inactive to active in the subsequent IOM-2 frame for at least one frame.
The transmitter indicates a new byte in the MON-slot by the transition of the MX-bit
from the active to the inactive state. The MX-bit returns to the active state after one
frame. Two frames with the MX-bit in the inactive state indicate the end of
transmission.
The receiver acknowledges each new byte by a similar one frame transition of the
MR-bit to the inactive state. Two frames with the MR-bit set to inactive indicate a
receiver request for abort.
The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence.
Delaying a transmission sequence is only possible while the receiver MR-bit and the
transmitter MX-bit are active.
Since the receiver is able to receive the MON-slot data at least twice (in two
consecutive frames), the receiver waits for the reception of two successive identical
bytes.
To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MON-data.
84
Operational Description