PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 137

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
Register 9
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
RDTB
RDRB
RDTA
RDRA
Bit
RDTB
7
Reset DMA Transmit Channel B
Reset DMA Receive Channel B
Reset DMA Transmit Channel A
Reset DMA Receive Channel A
Self-clearing command bit.
These bits bring the corresponding DMA channel to the reset state:
bit=’0’
bit=’1’
DTACK
DCMDR
DMA Command Register
TB
6
read/write
00
0C
written by CPU, evaluated by SEROCCO-D
H
H
RDRB
No reset is performed.
Reset is performed.
DMA Controller Reset Command Bits
5
DTACK
RB
5-137
4
RDTA
3
Register Description (DCMDR)
DTACK
TA
2
RDRA
1
PEB 20542
PEF 20542
2000-09-14
DTACK
RA
0