PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 258

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

6
6.1
After Reset the CPU has to write a minimum set of registers and an optional set
depending on the required features and operating modes.
First, the following initialization steps must be taken:
• Select serial protocol mode (refer to
• Select encoding of the serial data (refer to
• Program the output characteristics of
• Choose a clock mode (refer to
• Power-up the oscillator unit (with or without shaper) by re-setting bit GMODE:OSCPD
The clock mode must be set before power-up (CCR0H.PU). The CPU may switch the
SEROCCO-D between power-up and power-down mode. This has no influence upon the
contents of the registers, i.e. the internal state remains stored. In power-down mode
however, all internal clocks are disabled, no interrupts from the corresponding channel
are forwarded to the CPU. This state can be used as a standby mode, when the channel
is (temporarily) not used, thus substantially reducing power consumption.
The SEROCCO-D should usually be initialized in Power-Down mode.
The need for programming further registers depends on the selected features (serial
mode, clock mode specific features, operating mode, address mode, user demands).
6.2
6.2.1
In transmit direction 2 ´ 32 byte FIFO buffers (transmit pools) are provided for each
channel. After checking the XFIFO status by polling the Transmit FIFO Write Enable bit
(bit ’XFW’ in
bytes may be entered by the CPU into the XFIFO.
Data Sheet
Page
Page
- pin TxD (selected with bit ’ODS’ in
Byte)” on Page
- interrupt pin INT/INT (selected with bit field ’IPC(1:0)’ in
Page
to ’0’, if appropriate (GMODE:DSHP=’0’ enables the shaper).
86),
75),
127),
Programming
Initialization
Interrupt Mode
Data Transmission (Interrupt Driven)
STARL
159) and
register) or after a Transmit Pool Ready (’XPR’) interrupt, up to 32
Table 7 "Overview of Clock Modes" on Page
258
“Channel Configuration Register 1 (Low
Table 12 "Protocol Mode Overview" on
Chapter 3.2.13 “Data Encoding” on
“Global Mode Register” on
Programming
PEB 20542
PEF 20542
2000-09-14
48).