PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 209

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
In operating modes that provide address recognition, the high/low byte of the received
address is compared with the individually programmable values in register RAH2/
RAL2/RAH1/RAL1.
This addresses can be masked on a per bit basis by setting the corresponding bits in
registers
recognition. This feature is applicable to all HDLC sub-modes with address recognition.
RAH1
RAL1
RAH2
RAL2
AMRAL1/AMRAH1/AMRAL2/AMRAH2
Receive Address 1 Byte High
In HDLC Automode bit ’1’ is reserved for ’CRI’ (Command Response
Interpretation). In all other modes
CRI
The setting of this bit effects the meaning of the ’C/R’ bit in the receive
status byte (RSTA). This status bit ’C/R’ should be interpreted after
reception as follows:
’0’ (if ’CRI’=’1’) ;
’1’ (if ’CRI’=’1’) ;
Note: If 1-byte address field is selected in HDLC Automode,
Receive Address 1 Byte Low
The general function and its meaning depends on the selected HDLC
operating mode:
• Automode / Address Mode 2 (16-bit address)
• Automode / Address Mode 2 (8-bit address)
Receive Address 2 Byte High
Receive Address 2 Byte Low
Value of the second individually programmable high/low address byte. If
a 1-byte address field is selected,
a ’RESPONSE’ frame according to X.25 LAP-B protocol.
RAL1
address byte.
According to X.25 LAP-B protocol, the address in
as the address of a ’COMMAND’ frame.
be set to 0x00
can be programmed with the value of the first individual low
’1’ (if ’CRI’=’0’) :
’0’ (if ’CRI’=’0’) :
H
Command/Response Interpretation
.
5-209
RAL2
RAH1
to allow extended broadcast address
COMMAND received
RESPONSE received
is considered as the address of
is an 8 bit address.
Register Description (RAH2)
RAL1
is considered
(hdlc modes)
(hdlc modes)
(hdlc modes)
(hdlc modes)
PEB 20542
PEF 20542
RAH1
2000-09-14
must