PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 173

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
SLOAD
CSF
SUET
CHL(1:0)
RAC
Enable SYN Character Load
In BISYNC mode, SYN characters might be filtered out or stored to the
SCC receive FIFO.
SLOAD=’0’
SLOAD=’1’
Compare Status Field
This bit is only valid in HDLC SS7 mode:
If the status fields of consecutive LSSUs are equal, only the first will be
stored and every following is ignored
CSF=’0’
CSF=’1’
Signalling Unit Counter Threshold
This bit is only valid in HDLC SS7 mode:
Defines the number of signaling units received in error that will cause an
error rate high indication (ISR1.SUEX).
SUET=’0’
SUET=’1’
Character Length
This bit field selects the number of data bits within a character:
CHL = ’00’
CHL = ’01’
CHL = ’10’
CHL = ’11’
Receiver active
Switches the receiver between operational/inoperational states:
RAC=’0’
RAC=’1’
SYN characters are filtered out and not stored in the
receive FIFO.
All received characters, including SYN characters, are
stored in the receive FIFO.
Compare is disabled, all received LSSUs are stored in the
receive FIFO.
Compare is enabled, only the first one of consecutive
equal LSSUs is stored in the receive FIFO.
threshold is 64 errored signaling units.
threshold is 32 errored signaling units.
8-bit data.
7-bit data.
6-bit data.
5-bit data.
Receiver inactive, receive line is ignored.
Receiver active.
5-173
Register Description (CCR3H)
(async/bisync modes)
(bisync mode)
PEB 20542
PEF 20542
(hdlc mode)
(hdlc mode)
(all modes)
2000-09-14