PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 238

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
SYNCH(7:0) Synchronization Character (high)
SYNCL(7:0) Synchronization Character (low)
This register is only valid in BISYNC protocol mode.
The synchronization (SYN) character format depends on the setting of
bit ’BISNC’ and ’SLEN’ in register CCR2L:
• MONOSYNC Mode (CCR2L.BISNC = ’0’)
• BISYNC Mode (CCR2L.BISNC = ’1’)
In transmit direction the SYN character is sent continuously if no data
has to be transmitted and interframe timefill control is enabled by setting
bit ’ITF’ to ’1’ in register CCR2H.
In receive direction the receiver monitors the data stream for occurence
of the specified SYN pattern if operating in ’HUNT’ mode (bit ’HUNT’ in
register CMDRH).
The SYN character is defined by register ’SYNCL’:
a) SLEN = ’0’: the 6 bit SYN character is specified by bits (5..0)
b) SLEN = ’1’: the 8 bit SYN character is specified by bits (7..0).
The SYN character is defined by registers ’SYNCL’ and ’SYNCH’:
a) SLEN = ’0’: the 12 bit SYN character is specified by bits (5..0) of
each register, i.e. SYN(11..0) = SYNCH(5:0), SYNCL(5:0)
b) SLEN = ’1’: the 16 bit SYN character is specified by bits (7..0) of
each register, i.e. SYN(15..0) = SYNCH(7:0), SYNCL(7:0).
238
Register Description
(bisync mode)
(bisync mode)
PEB 20542
PEF 20542
2000-09-14