ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 141
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.11.7
12.11.8
8210B–AVR–04/10
INTCTRLB - Interrupt Enable Register B
CTRLFCLR/CTRLFSET - Control Register F Clear/Set
• Bit 3:2 - ERRINTLVL[1:0]:Timer Error Interrupt Level
These bits enable the Timer Error Interrupt and select the interrupt level as described in
rupts and Programmable Multi-level Interrupt Controller” on page
• Bit 1:0 - OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level
These bits enable the Timer Overflow/Underflow Interrupt and select the interrupt level as
described in
• Bit 7:0 - CCxINTLVL[1:0] - Compare or Capture x Interrupt Level:
These bits enable the Timer Compare or Capture Interrupt and select the interrupt level as
described in
This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for
setting the register bits (CTRLxSET) when written. Both memory locations yield the same result
when read.
The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared
by writing a one to its bit location in CTRLxCLR. This each bit to be set or cleared without using
of a Read-Modify-Write operation on a single register.
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - CMD[1:0]: Timer/Counter Command
These command bits can be used for software control of update, restart, and reset of the
Timer/Counter. The command bits are always read as zero.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
”Interrupts and Programmable Multi-level Interrupt Controller” on page
”Interrupts and Programmable Multi-level Interrupt Controller” on page
R/W
CCDINTLVL[1:0]
7
0
R
R
7
–
0
7
–
0
R/W
R
R
6
0
6
–
0
6
–
0
R/W
R
R
5
–
0
5
–
0
5
CCCINTLVL[1:0]
0
R
4
–
0
4
–
R
0
R/W
4
0
R/W
R
3
0
3
0
R/W
CMD[1:0]
CMD[1:0]
CCBINTLVL[1:0]
3
0
R/W
R
2
0
2
0
R/W
2
0
95.
LUPD
LUPD
R/W
R/W
1
0
1
0
R/W
CCAINTLVL[1:0]
1
0
R/W
R/W
DIR
DIR
XMEGA D
0
0
0
0
R/W
0
0
95.
95.
CTRLFCLR
CTRLFSET
INTCTRLB
”Inter-
141
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