ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 184
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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16.9.4
8210B–AVR–04/10
STATUS - Master Status Register
• Bit 7 - RIF: Read Interrupt Flag
This Read Interrupt Flag (RIF) is set when a byte is successfully received in Master Read mode,
i.e. no arbitration lost or bus error occurred during the operation. Writing a one to this bit location
will clear the RIF. When this flag is set the master forces the SCL line low, stretching the TWI
clock period. Clearing the interrupt flags will release the SCL line.
This flag is also automatically cleared when:
• Bit 6 - WIF: Write Interrupt Flag
The Write Interrupt Flag (WIF) flag is set when a byte is transmitted in Master Write mode. The
flag is set regardless of the occurrence of a bus error or an arbitration lost condition. The WIF is
also set if arbitration is lost during sending of NACK in Master Read mode, and if issuing a
START condition when the bus state is unknown. Writing a one to this bit location will clear the
WIF. When this flag is set the master forces the SCL line low, stretching the TWI clock period.
Clearing the interrupt flags will release the SCL line.
The flag is also automatically cleared for the same conditions as RIF.
• Bit 5 - CLKHOLD: Clock Hold
The master Clock Hold (CLKHOLD) flag is set when the master is holding the SCL line low. This
is a status flag, and a read only bit that is set when the RIF and WIF is set. Clearing the interrupt
flags and releasing the SCL line, will indirectly clear this flag.
The flag is also automatically cleared for the same conditions as RIF.
• Bit 4 - RXACK: Received Acknowledge
The Received Acknowledge (RXACK) flag contains the most recently received acknowledge bit
from slave. This is a read only flag. When read as zero the most recent acknowledge bit from the
slave was ACK, and when read as one the most recent acknowledge bit was NACK.
• Bit 3 - ARBLOST: Arbitration Lost
The Arbitration Lost (ARBLOST) flag is set if arbitration is lost while transmitting a high data bit,
a NACK bit, or while issuing a START or Repeated START condition on the bus. Writing a one
to this bit location will clear the ARBLOST flag.
Writing the ADDR register will automatically clear the ARBLOST flag.
Bit
+0x03
Read/Write
Initial Value
• Writing to the ADDR register.
• Writing to the DATA register.
• Reading the DATA register.
• Writing a valid command to the CMD bits in the CTRLC register.
R/W
RIF
7
0
WIF
R/W
6
0
CLKHOLD
R/W
5
0
RXACK
R/W
4
0
ARBLOST
R/W
3
0
BUSERR
R/W
2
0
R/W
1
0
BUSSTATE[1:0]
XMEGA D
R/W
0
0
STATUS
184
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