ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 63
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Price
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101
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ATxmega192D3-H
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SQ
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Quantity:
565
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6.9
6.9.1
6.9.2
8210B–AVR–04/10
Register Description - Clock
CTRL - System Clock Control Register
PSCTRL - System Clock Prescaler Register
• Bit 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2:0 - SCLKSEL[2:0]: System Clock Selection
SCLKSEL is used to select the source for the System Clock. See
selections. Changing the system clock source will take 2 clock cycles on the old clock source
and 2 clock cycles on the new clock source. These bits are protected by the Configuration
Change Protection mechanism, for details refer to
12.
SCLKSEL cannot be changed if the new source is not stable.
Table 6-1.
• Bit 7 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
SCLKSEL[2:0]
000
001
010
011
100
101
110
111
R
7
–
0
System Clock Selection
R
7
–
0
R/W
6
0
6
–
R
0
R/W
5
0
Group Configuration
R
5
–
0
RC32MHz
RC32KHz
PSADIV[4:0]
RC2MHz
XOSC
PLL
R/W
4
0
-
-
-
R
4
–
0
R/W
”Configuration Change Protection” on page
3
0
R
3
–
0
Description
External Oscillator or Clock
Phase Locked Loop
Reserved
Reserved
Reserved
2 MHz Internal RC Oscillator
32 MHz Internal RC Oscillator
32.768 kHz Internal RC Oscillator
R/W
R/W
2
0
2
0
SCLKSEL[2:0]
Table 6-1
R/W
R/W
1
0
1
0
PSBCDIV
XMEGA D
R/W
for the different
R/W
0
0
0
0
PSCTRL
CTRL
63
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