ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 71
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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6.11
6.11.1
6.11.2
6.11.3
8210B–AVR–04/10
Register Description - DFLL32M/DFLL2M
CTRL - DFLL Control Register
CALA - Calibration Register A
CALB - Calibration Register B
• Bit 7:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator
CALA and CALB register holds the 13 bit DFLL calibration value that is used for automatic run-
time calibration the internal oscillator. When the DFLL is disabled, the calibration registers can
be written by software for manual run-time calibration of the oscillator. The oscillators will be cal-
ibrated according to the calibration value in these registers also when the DFLL is disabled.
• Bit 7:0 - CALL[7:0]: DFLL Calibration bits
These bits hold the 7 Least Significant Bits (LSB) of the calibration value for the oscillator. After
reset CALL is set to its middle value, and during automatic runtime calibration of the oscillator
these bits are use to change the oscillator frequency. The bits are controlled by the DFLL when
the DFLL is enabled.
• Bit 7:5 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
R/W
R
7
0
7
–
0
7
–
R
0
R/W
R
6
1
6
–
0
R
6
–
0
R/W
5
–
R
0
5
0
R
5
–
0
R/W
R/W
R
4
0
4
–
0
4
x
CALL[7:0]
R/W
R/W
R
3
0
3
–
0
3
x
CALH[12:8]
R/W
R/W
R
2
–
0
2
0
2
x
R/W
R/W
R
1
–
0
1
0
1
x
XMEGA D
ENABLE
R/W
R/W
R/W
0
0
0
0
0
x
CTRL
CALA
CALB
71
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