ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 77

• Manufacturer Part Number: ATxmega192D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega192D3

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6
7.6.1
7.6.2
8210B–AVR–04/10
Register Description – Power Reduction
PRGEN - General Power Reduction Register
PRPA/B - Power Reduction Port A/B Register
Table 7-2.
• Bit 1 - SEN: Sleep Enable
This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruc-
tion is executed. To avoid unintentional entering of sleep modes, it is recommended to write
SEN just before executing the SLEEP instruction, and clearing it immediately after waking up.
• Bit 7:3 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 - RTC: Real-Time Counter
Setting this stops the clock to the Real Time Counter. When the bit is cleared the peripheral
should be reinitialized to ensure proper operation.
• Bit 1 - EVSYS: Event System
Setting this stops the clock to the Event System. When the bit is cleared the module will continue
like before the shutdown.
• Bit 0 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
Note:
Bit
+0x01/+0x02
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
SMODE[2:0]
Disabling of analog modules stops the clock to the analog blocks themselves and not only the
interfaces.
101
110
111
R
7
–
0
R
Sleep mode
7
–
0
R
6
–
0
R
6
–
0
SEN
1
1
1
R
5
–
0
R
5
–
0
R
R
4
–
0
4
–
0
Group Configuration
ESTDBY
STDBY
R
3
–
R
0
3
–
0
-
RTC
R/W
R
2
–
0
2
0
EVSYS
ADC
R/W
R/W
Description
Reserved
Standby Mode
Extended Standby Mode
1
0
1
0
XMEGA D
R/W
AC
R
0
0
0
–
0
PRGEN
PRPA
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