ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 197
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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17.6.2
17.6.3
8210B–AVR–04/10
INTCTRL - SPI Interrupt Control Register
STATUS - SPI Status Register
The relationship between SCK and the Peripheral Clock frequency (clk
4 on page
Table 17-4.
• Bits 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 1:0 - INTLVL[1:0]: SPI Interrupt Level
These bits enable the SPI Interrupt and select the interrupt level as described in
Programmable Multi-level Interrupt Controller” on page
gered when the IF in the STATUS register is set.
• Bit 7 - IF: SPI Interrupt Flag
When a serial transfer is complete and one byte is completely shifted in/out of the DATA regis-
ter, the IF bit is set. If SS is an input and is driven low when the SPI is in Master mode, this will
also set the IF bit. The IF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, the SPIF bit can be cleared by first reading the STATUS register
with IF set, and then access the DATA register.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
CLK2X
0
0
0
0
1
1
1
1
197.
IF
7
–
R
0
R
7
0
Relationship Between SCK and the Peripheral Clock (clk
WCOL
6
–
R
0
R
6
0
PRESCALER[1:0]
R
R
5
–
0
5
–
0
00
01
10
11
00
01
10
11
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
SCK Frequency
clk
clk
clk
clk
clk
clk
clk
clk
PER
PER
PER
PER
PER
PER
PER
PER
95. The enabled interrupt will be trig-
/4
/16
/64
/128
/2
/8
/32
/64
R
R
2
–
0
2
–
0
PER
R/W
PER
R
1
0
1
–
0
INTLVL[1:0]
)is shown in
) frequency
XMEGA D
R/W
”Interrupts and
R
0
0
0
–
0
Table 17-
INTCTRL
STATUS
197
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