ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 201
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18.3
18.3.1
8210B–AVR–04/10
Clock Generation
Internal Clock Generation - The Fractional Baud Rate Generator
The clock used for baud rate generation, and for shifting and sampling data bits is generated
internally by the Fractional Baud Rate Generator or externally from the Transfer Clock (XCK)
pin. Five modes of clock generation are supported: Normal and Double Speed asynchronous
mode, Master and Slave synchronous mode, and Master SPI mode.
Figure 18-2. Clock Generation Logic, Block Diagram.I
The Fractional Baud Rate Generator is used for internal clock generation for asynchronous
modes, synchronous master mode, and SPI master mode operation. The generated output fre-
quency (f
Peripheral Clock frequency (f
baud rate (in bits per second) and for calculating the BSEL value for each mode of operation.
BSEL can be set to any value between 0 and 4095. It also show the maximum baud rate versus
peripheral clock speed.
Fractional baud rate generation can be used in asynchronous mode of operation to increase the
average resolution. A scale factor (BSCALE) allows the baud rate to be optionally left or right
scaled. Choosing a positive scale value will results in right scaling, which increase the period
and consequently reduce the frequency of the produced baud rate, without changing the resolu-
tion. If the scale value is negative the divider uses fractional arithmetic counting to increase the
resolution by distributing the fractional divide value over time. BSCALE can be set to any value
from -7 to +7, where 0 implies no scaling. There is a limit to how high the scale factor can be and
the value 2
see
PORT_INV
DDR_XCK
XCK
Pin
Section 18.9 on page 210
BAUD
BSCALE
xcko
xcki
) is given by the period setting (BSEL), an optional scale setting (BSACLE) and the
f
OSC
must be at least half of the minimum number of clock cycles a frame takes,
Baud Rate
Generator
Register
BSEL
Sync
PER
for more details.
).
f
BAUD
Table 18-1 on page 202
Detector
Edge
/2
/4
contains equations for calculating the
/2
DDR_XCK
CLK2X
XMEGA D
0
1
0
1
0
1
1
0
UMSEL [1]
txclk
rxclk
201
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