ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 269
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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22.6
22.6.1
22.6.2
22.6.3
8210B–AVR–04/10
Register Description - PDI Control and Status Register
STATUS - Program and Debug Interface Status Register
RESET - Program and Debug Interface Reset register
CTRL - Program and Debug Interface Control Register
These register are registers that are accessible in the PDI Control and Status Register Space
(CSRS) using the instructions LDCS and STCS. The CSRS is allocated for registers directly
involved in configuration and status monitoring of the PDI itself.
• Bit 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1- NVMEN: Non-Volatile Memory Enable
This status bit is set when the key signalling enables the NVM programming interface. The
External Programmer can poll this bit to verify successful enabling. Writing the NVMEN bit dis-
ables the NVM interface
• Bit 0 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 7:0 - RESET[7:0]: Reset Signature
When the Reset Signature - 0x59 - is written to RESET, the device is forced into reset. The
device is kept in reset until RESET is written with a data value different from the Reset Signature
(0x00 is recommended). Reading the least LSB bit the will return the status of the RESET. The 7
MSB bits will always return the value 0x00 regardless of whether the device is in reset or not.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
R/W
R
R
7
–
0
7
0
7
–
0
R/W
R
R
6
–
0
6
0
6
–
0
R/W
R
R
5
–
0
5
0
5
–
0
R/W
R
R
4
–
0
4
0
4
–
0
RESET[7:0]
R/W
R
R
3
–
0
3
0
3
–
0
R/W
R/W
R
2
–
0
2
0
2
0
GUARDTIME[2:0]
NVMEN
R/W
R/W
R
1
0
1
0
1
0
XMEGA D
R/W
R/W
R
0
–
0
0
0
0
0
STATUS
CTRLB
CTRL
269
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