MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 12

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Reset and Configuration Signals
1.3 Reset and Configuration Signals
1.4 Direct Slave Interface, System Bus, and Interrupt
1-4
Signals
The direct slave interface (DSI) is combined with the system bus because they share some common
signal lines. Individual assignment of a signal to a specific signal line is configured through internal
registers. Table 1-5 describes the signals in this group.
Note:
Signal Name
PORESET
RSTCONF
HRESET
SRESET
Note:
Signal Name
HD0
SWTE
HD1
DSISYNC
Although there are fifteen interrupt request (IRQ) connections to the core processors, there are
multiple external lines that can connect to these internal signal lines. After reset, the default
configuration enables only IRQ[1–7], but includes two input lines each for IRQ[1–3] and
IRQ7. The designer must select one line for each required interrupt and reconfigure the other
external signal line or lines for alternate functions. Additional alternate IRQ lines and
IRQ[8–15] are enabled through the GPIO signal lines.
When PORESET is deasserted, the MSC8102 also samples the following signals:
Refer to Table 1-5 for details on these signals.
• BM[0–2]—Selects the boot mode.
• MODCK[1–2]—Selects the clock configuration.
• SWTE—Enables the software watchdog timer.
• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.
Output
Output
Type
Type
Input/
Input/
Input
Input
Input
Input
Input
Input
Table 1-5. DSI, System Bus, and Interrupt Signals
Power-On Reset
When asserted, this line causes the MSC8102 to enter power-on reset state.
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function
is provided in the MSC8102 Reference Manual. This signal is sampled upon deassertion
of PORESET.
Hard Reset
When asserted, this open-drain line causes the MSC8102 to enter hard reset state.
Soft Reset
When asserted, this open-drain line causes the MSC8102 to enter soft reset state.
Host Data Bus 0
Bit 0 of the DSI data bus.
Software Watchdog Timer Disable.
It is sampled on the rising edge of PORESET signal.
Host Data Bus 1
Bit 1 of the DSI data bus.
DSI Synchronous
Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled
on the rising edge of PORESET signal.
Table 1-4. Reset and Configuration Signals
1
Signal Description
Description