MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 30

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

EOnCE Event and JTAG Test Access Port Signals
1.7 EOnCE Event and JTAG Test Access Port Signals
1.8 Reserved Signals
1-22
The MSC8102 uses two sets of debugging signals for the two types of internal debugging modules:
EOnCE and the JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all
accessed externally by the same two signals EE0 and EE1. The MSC8102 supports the standard set of
Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan
Architecture specification and described in Table 1-8.
Signal Name
EE0
EE1
TCK
TDI
TDO
TMS
TRST
Signal Name
TEST
Output
Output
Type
Type
Input
Input
Input
Input
Input
Input
EOnCE Event Bit 0
Used for putting the internal SC140 cores into Debug mode.
EOnCE Event Bit 1
Indicates that at least one on-chip SC140 core is in Debug mode.
Test Clock—A test clock signal for synchronizing JTAG test logic.
Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on
the rising edge of TCK and has an internal pull-up resistor.
Test Data Output—A test data serial signal for test instructions and data. TDO can be
tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
Test Mode Select—Sequences the test controller’s state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor.
Test Reset—Asynchronously initializes the test controller, has an internal pull-up resistor,
and must be asserted after power up.
Test
Used for manufacturing testing. You must connect this pin to GND.
Table 1-8. JTAG Test Access Port Signals
Table 1-9. Reserved Signals
Signal Description
Signal Description