MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 7

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

• Timers
• Hardware semaphores. Eight coded hardware semaphores, locked by simple write access without need
• General-Purpose I/O (GPIO) port:
• Global Interrupt Controller (GIC):
• Software support, with support from industry-leading third parties:
— Single-wire and loop operations.
— Two modules of 16 timers each.
— Each timer has the following features:
— Watchdog mode for the timers that connect to the device.
for read-modify-write mechanism.
— 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.
— Each port can be programmed separately to serve up to two dedicated peripherals, and each port
— Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to
— Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.
— Generation of virtual NMI (one to each SC140 core) by a simple write access.
— Real-Time Operating Systems (RTOS):
— Integrated Development Environment (IDE):
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supports open-drain output mode.
INT_OUT, NMI_OUT, and to the cores.
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Cyclic or one-shot.
Input clock polarity control.
Interrupt request when counting reaches a programmed threshold.
Pulse or level interrupts.
Dynamically updated programmed threshold.
Read counter any time.
Fully supports MSC8102 device architecture (multi-core, memory hierarchy, ICache, timers,
DMA, interrupts, peripherals).
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Multi-core support:
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Distributed system support, enables transparent inter-task communications between tasks
running inside the SC140 cores and the other tasks running on devices on the board or remote
devices in the network
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Additional features:
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High-performance and deterministic, delivering predictive response time.
Optimized to provide low interrupt latency with high data throughput.
Preemptive and priority-based multitasking.
Fully interrupt/event driven.
Small memory footprint.
Comprehensive set of APIs.
Fully supports MSC8102 DMA, interrupts, and timer schemes.
Enables use of one instance of kernel code all four SC140 cores.
Dynamic and static memory allocation from local memory (M1) and shared memory
(M2).
Messaging mechanism between tasks using mailboxes and semaphores.
Networking support; data transfer between tasks running inside and outside the device
using networking protocols.
Includes integrated device drivers for such peripherals as TDM, UART, and external
buses.
Incorporates task debugging utilities integrated with compilers and vendors.
Board support package (BSP) for MSC8102ADS.
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