MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 13

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Signal Name
HD2
DSI64
HD3
MODCK1
HD4
MODCK2
HD5
CNFGS
HD[6–31]
HD[32–63]
D[32–63]
HCID[0–3]
HA[11–29]
HWBS[0–3]
HDBS[0–3]
HWBE[0–3]
HDBE[0–3]
Input/O
Input/O
Input/O
Output
Output
Output
Output
Type
Input/
Input/
Input/
Input/
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Input
Input
Input
Input
utput
utput
utput
Input
Input
Input
Input
Input
Input
Host Data Bus 2
Bit 2 of the DSI data bus.
DSI 64
Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of
PORESET signal.
Host Data Bus 3
Bit 3 of the DSI data bus.
Clock Mode 1
Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
Host Data Bus 4
Bit 4 of the DSI data bus.
Clock Mode 2
Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
Host Data Bus 5
Bit 5 of the DSI data bus.
Configuration Source
One signal out of two that indicates reset configuration mode. It is sampled on the rising
edge of PORESET signal.
Host Data Bus 6–31
Bits 6–31 of the DSI data bus.
Host Data Bus 32–63
Bits 32–63 of the DSI data bus.
System Bus Data 32–63
In write transactions, the bus master drives the valid data on this bus. In read transactions,
the slave drives the valid data on this bus.
Host Chip ID 0–3
Carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]
matches the Chip_ID, or if HBCS is asserted.
Host Bus Address 11–29
Used by external host to access the internal address space.
Host Write Byte Strobes (In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host read or write accesses.
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host write accesses
Direct Slave Interface, System Bus, and Interrupt Signals
Description
1-5