MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 15

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Signal Name
A[0–31]
TT0
TT1
TT[2–4]
CS[5–7]
CS[0–4]
TSZ[0–3]
TBST
IRQ1
GBL
IRQ3
BADDR31
IRQ2
BADDR30
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input/
Input/
Input/
Input/
Input/
Input/
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Input
Input
Input
Address Bus
When the MSC8102 is in external master bus mode, these pins function as the system
address bus. The MSC8102 drives the address of its internal bus masters and responds to
addresses generated by external bus masters. When the MSC8102 is in internal master
bus mode, these pins are used as address lines connected to memory devices and are
controlled by the MSC8102 memory controller.
Bus Transfer Type 0
The bus master drives this pins during the address tenure to specify the type of the
transaction.
Bus Transfer Type 1
The bus master drives this pins during the address tenure to specify the type of the
transaction. Some applications use only the TT1 signal, for example, from MSC8102 to
MSC8102 or MSC8102 to MSC8101 and vice versa. In these applications, TT1 functions
as read/write signal.
Bus Transfer Type 2–4
The bus master drives these pins during the address tenure to specify the type of the
transaction.
Chip Select 5–7
Enables specific memory devices or peripherals connected to the system bus.
Chip Select 0–4
Enables specific memory devices or peripherals connected to the system bus.
Transfer Size 0–3
The bus master drives these pins with a value indicating the number of bytes transferred in
the current transaction.
Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst
transaction (transfers eight words).
Interrupt Request 1
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Global
When a master within the MSC8102 initiates a bus transaction, it drives this pin. Assertion
of this pin indicates that the transfer is global and should be snooped by caches in the
system.
Interrupt Request 3
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Burst Address 31
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
Interrupt Request 2
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Burst Address 30
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
1
Direct Slave Interface, System Bus, and Interrupt Signals
1
1
1
1
1
Description
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