MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 44

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

AC Timings
2.6.5 DSI Timing
2-14
Notes:
No.
100
101
102
103
104
105
106
107
108
109
110
111
112
201
202
Attributes
Attributes
Read/Write data strobe deassertion width
•
•
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedance
Output data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedance
Output data valid to HTA assertion
Read/Write data strobe assertion to HTA valid
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
•
•
•
Read/Write data strobe assertion width
Host data input setup time before write data strobe deassertion
Host data input hold time after write data strobe deassertion
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
1.
“Attributes” refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
The timings in the following sections are based on a 30 pF capacitive load. See Section 2.6.1, Load
Assumptions, on page 5 for more details.
2.6.5.1 DSI Asynchronous Mode
1
1
setup time before strobe (HWBS[n]) assertion
hold time after data strobe deassertion
Characteristics
Table 2-18. DSI Asynchronous Mode Timing
2
5 + (1.5
5 + (2.5
1.8 + T
1.8 + T
1.8 + T
5 + T
Min
3.6
2.4
3.8
2.2
3.9
1.3
—
—
—
—
—
REFCLK
1
2
REFCLK
REFCLK
REFCLK
T
T
REFCLK
REFCLK
)
)
5 + (1.5
5 + (2.5
5 + T
Max
7.8
9.8
6.5
9.2
—
—
—
—
—
—
—
—
—
—
REFCLK
T
T
REFCLK
REFCLK
)
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns