MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 94

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Connectivity Guidelines
4.3 Connectivity Guidelines
4-2
Voltage Regulator
Power supply
(I
min
or
= 3 A)
Figure 4-2 shows the recommended power decoupling circuit for the core power supply. The voltage
regulator and the decoupling capacitors should supply the required device current without any drop in
voltage on the device pins. The voltage on the package pins should not drop below 1.5 V even for a very
short spikes. This can be achieved by using the following guidelines:
• For the core supply, use a voltage regulator rated at 1.6 V with nominal rating of at least 3 A.
• Decouple the supply using low-ESR capacitors mounted as close as possible to the socket.
Figure 4-2 shows three capacitors in parallel to reduce the resistance. Three capacitors is a recommended
minimum number.
Unused output pins can be disconnected, and unused input pins should be connected to there non-active
value, except for the following:
• If the DSI is unused (Bit DDR[1]:DSIDIS is set), then
• When the DSI uses Synchronous mode,
•
• When the DSI is in 64-bit Data bus mode and DCR[2]:BEM is cleared, the
• When the DSI is in 32-bit Data bus mode and DCR[2] (BEM) is cleared,
• When the DSI is in Asynchronous mode,
• The following signals can be disconnected in single-master mode (BCR[EBM] is reset):
• The following signals must be pulled up:
rest of the DSI signals can be disconnected.
pulled either up or down depending on design requirements.
HDST
DCR[7]:DSRFA bit is set.
HWBS[1–3]
HWBS[4–7]
V
HWBS[1–3]
V
EXT_BG[2–3]
DD
DD
.
.
+
-
1.6 V
can be disconnected if the DSI is in Big-endian mode, or if the DSI is in Little-endian mode and
/
/
/
Figure 4-2. Core Power Supply Decoupling
HDBS[1–3]
HDBS[4–7]
HDBS[1–3]
,
EXT_DBG[2-3]
Bulk/Tantalum capacitors
with low ESR and ESL
/
/
/
HWBE[1–3]
HWBE[4–7]
HWBE[1–3]
Capacitors of 150 f
,
GBL
maximum IR drop
of 15 mV at 1 A
/
/
/
and
HDBE[1–3]
HDBE[4–7]
HDBE[1–3]
HTA
TS
HRESET
HBRST
.
must be pulled up. In asynchronous mode,
/
and
must be tied to
PWE[4–7]
and
,
SRESET
HCLKIN
L
HCS
max
/
= 2 cm
PSDDQM[4–7]
and
,
ARTRY
should either be disconnected or tied to
V
HBCS
DD
.
,
TA
must be tied to
One 0.01 mF capacitor
for every 3 Core supply
(very low ESR and ESL)
pads.
High Freq. capacitors
,
/
TEA
PBS[4–7]
,
PSDVAL
must be tied to
V
HTA
DD
BG
, and
MSC8102
and all the
,
should be
DBG
AACK
,
.