MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 45

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MSC8102D

Manufacturer Part Number
MSC8102D
Description
Quad Core 16-Bit Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
Figure 2-5 shows DSI Asynchronous Read signals timing.
HA[11–29]
HCID[0–4]
Notes:
HWBSn
HD[0–63]
HDBSn
Figure 2-5. Asynchronous Single and Dual Modes Read Timing Diagram
HRDS
HTA
HTA
HRW
HDST
HCS
3
4
2
1
1
2
1.
2.
3.
4.
Used for Single Strobe mode access.
Used for Dual Strobe mode access.
HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with
pull-down implementation.
HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up
implementation.
108
104
106
100
107
112
103
105
101
102
111
109
110
2-15

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