MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 19

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Signal Name
IRQ7
DP7
DREQ4
TA
TEA
NMI
NMI_OUT
PSDVAL
IRQ7
INT_OUT
Notes:
1.
2.
See the System Interface Unit (SIU) chapter in the MSC8102 Reference Manual for details on how to
configure these pins.
When used as the bus control arbiter, the MSC8102 can support up to three external bus masters.
Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG,
EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets
must be configured to indicate whether the external master is or is not a MSC8102 master device. See
the Bus Configuration Register (BCR) description in the System Interface Unit (SIU) chapter in the
MSC8102 Reference Manual for details on how to configure these pins. The second and third set of
pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The
first set of pins (BR/BG/DBG) have a dual function. When the MSC8102 is not the bus arbiter, these
signals (BR/BG/DBG) are used by the MSC8102 to obtain master control of the bus.
Output
Output
Output
Output
Output
Output
Type
Input/
Input/
Input/
Input/
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Input
Input
Input
Input
Interrupt Request 7
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
System Bus Data Parity 7
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 7 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 7 and D[56–63].
DMA Request 4
Used by an external peripheral to request DMA service.
Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion
indicates the termination of the transfer. For burst transfers, TA is asserted eight times to
indicate the transfer of eight data beats, with the last assertion indicating the termination of
the burst transfer.
Transfer Error Acknowledge
Assertion indicates a failure of the data tenure transaction.The masters within the
MSC8102 monitor the state of this pin. The MSC8102 internal bus monitor can assert this
pin if it identifies a bus transfer that does not complete.
Non-Maskable Interrupt
When an external device asserts this line, it generates an non-maskable interrupt in the
MSC8102, which is processed internally (default) or is directed to an external host for
processing (see NMI_OUT).
Non-Maskable Interrupt Output
An open-drain pin driven from the MSC8102 internal interrupt controller. Assertion of this
output indicates that a non-maskable interrupt is pending in the MSC8102 internal interrupt
controller, waiting to be handled by an external host.
Port Size Data Valid
Indicates that a data beat is valid on the data bus. The difference between the TA pin and
the PSDVAL pin is that the TA pin is asserted to indicate data transfer terminations, while
the PSDVAL signal is asserted with each data beat movement. When TA is asserted,
PSDVAL is always asserted. However, when PSDVAL is asserted, TA is not necessarily
asserted. For example, if the DMA initiates a double word (2
memory device with a 32-bit port size, PSDVAL is asserted three times without TA and,
finally, both pins are asserted to terminate the transfer.
Interrupt Request 7
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Interrupt Output
Assertion of this output indicates that an unmasked interrupt is pending in the MSC8102
internal interrupt controller.
Direct Slave Interface, System Bus, and Interrupt Signals
Description
64 bits) transaction to a
1-11