MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 20

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Memory Controller Signals
1.5 Memory Controller Signals
1-12
Refer to the Memory Controller chapter in the MSC8102 Reference Manual for detailed information
about configuring these signals.
Signal Name
BCTL0
BCTL1
CS5
BM[0–2]
TC[0–2]
BNKSEL[0–2]
ALE
PWE[0–3]
PSDDQM[0–3]
PBS[0–3]
PSDA10
PGPL0
PSDWE
PGPL1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input/
Input
System Bus Buffer Control 0
Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin
is defined by the value of SIUMCR[BCTLC].
System Bus Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin
is defined by the value of SIUMCR[BCTLC].
System and Local Bus Chip Select 5
Enables specific memory devices or peripherals connected to MSC8102 buses.
Boot Mode 0–2
Defines the boot mode of the MSC8102. This signal is sampled on PORESET deassertion.
Transfer Code 0–2
The bus master drives these pins during the address tenure to specify the type of the
code.
Bank Select 0–2
Selects the SDRAM bank when the MSC8102 is in 60x-compatible bus mode.
Address Latch Enable
Controls the external address latch used in an external master bus.
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte
lanes for write operations.
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM
devices.
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during
memory operations. The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port size of the
accessed device.
System Bus SDRAM A10
From the bus SDRAM controller. The precharge command defines which bank is
precharged. When the row address is driven, it is a part of the row address. When column
address is driven, it is a part of column address.
System Bus UPM General-Purpose Line 0
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
From the bus SDRAM controller. Should connect to SDRAM WE input.
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
System Bus SDRAM Write Enable
System Bus UPM General-Purpose Line 1
Table 1-6. Memory Controller Signals
Description