MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 95

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

4.4 Power Considerations
Equation 2: P = C
• In single master mode,
• If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set,
• The following signals:
• The following signals: CHIPID[0–3], RSTCONF and BM[0–2] are used to configure the MSC8102
• The
• When they are used,
Note:
The internal power dissipation consists of three components:
The power dissipation depends on the operating frequency of the different portions of the chip. To
determine the power dissipation at a given frequency, the following equations should be applied:
To determine a total power dissipation in a specific application, the following equation should be applied
for each I/O output pin:
value. In other modes, they must be pulled up.
Otherwise, it should be pulled up.
MSC8102 and are sampled on the deassertion of the
to
PORESET
and are sampled at the deassertion of the PORESET signal. Therefore, they should be tied to GND or
VCC either directly or through a pull-down or a pull-up resistor.
BCR[EBM] bit is set.
drive) signals must be pulled up.
P
P
P
P
P
P
Where,
Where:
TCORE
INT
CORE
SIU
PERIPH
BUSES
GND
BR
(f
= P
For details on configuration, see the MSC8102 User’s Guide and MSC8102 Reference Manual.
f
P
P
P
P = power in mW
C = load capacitance in pF
f
c
s
,
c
V
(f
LCO
LSI
LPE
or
) = ((P
BG
(f
= output switching frequency in MHz.
is the operating frequency in MHz and all power numbers are in mW
(f
TCORE
(f
c
DDH
) = ((P
c
c
V
signal.
c
) = P
) = (P
is the SIU leakage power
,
) = ((P
DD
is the peripheral leakage power
is the SC140 Core leakage power
DBG
2
SIU
either directly or through a pull-down or a pull-up resistor until the deassertion of the
BUSES
+ P
CORE
CORE
,
PERIPH
f
– P
EXT_BR[2–3]
s
SIU
INT_OUT
LSI
SWTE
– P
ABB
/91.67
+ P
10
)/91.67)
4)
– P
LCO
–3
BUSES
and
,
LPE
)/275)
DSISYNC
(if SIUMCR[INTODC] is cleared),
f
DBB
)/91.67)
c
,
+ P
EXT_BG[2–3]
f
c
PERIPH
can be selected as
+ P
f
c
,
+ P
LSI
DSI64
f
c
LCO
+ P
,
,
LPE
EXT_DBG[2–3]
MODCK[1–2],
PORESET
IRQ
inputs and be connected to the non-active
signal. Therefore, they should be tied
and
, and
NMI_OUT
CNFGS
TS
PPBS
must be pulled up if the
are used to configure the
, and
can be disconnected.
IRQxx
(if not full
4-3