MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 47

no-image

MSC8102D

Manufacturer Part Number
MSC8102D
Description
Quad Core 16-Bit Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
Figure 2-7 shows DSI Asynchronous Broadcast Write signals timing.
HA[11–29]
HCID[0–4]
HD[0–63]
HWBSn
HDBSn
HRDS
Notes:
HRW
HDST
HTA
HTA
HCS
2
1
1
2
3
4
Figure 2-7. Asynchronous Broadcast Write Timing Diagram
1.
2.
3.
4.
Used for Single Strobe mode access.
Used for Dual Strobe mode access.
HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with
pull-down implementation.
HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up
implementation.
100
108
106
112
201
202
111
101
102
109
110
2-17

Related parts for MSC8102D