MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 40

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

AC Timings
2.6.4 System Bus Access Timing
2-10
Notes:
Notes:
No.
No.
10
11
12
13
14
15
16
10
11
12
13
14
15
16
Hold time for all signals after REFCLK rising edge
AACK/ARTRY/TA/TEA/DBG/BG/BR/PSDVAL setup time before REFCLK rising edge
Data bus setup time before REFCLK rising edge in Normal mode
Data bus setup time before REFCLK rising edge in ECC and PARITY modes
DP setup time before REFCLK rising edge
Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL setup time before REFCLK rising edge
Setup time before REFCLK rising edge for all other pins
Hold time for all signals after REFCLK rising edge
AACK/ARTRY/TA/TEA/DBG/BG/BR setup time before REFCLK rising edge
Data bus setup time before REFCLK rising edge in Normal mode
Data bus setup time before REFCLK rising edge in ECC and Parity modes
DP setup time before REFCLK rising edge
Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL setup time before REFCLK rising edge
Setup time before REFCLK rising edge for all other pins
1.
2.
1.
2.
Values are measured from the TTL signal level (0.8 or 2.0 V) relative to the REFCLK rising edge.
SIU inputs are for the normal configuration (SIUBCR[EXDD] = 0—which gives an extra cycle for address inputs. When
SIUBCR[EXDD] = 1, address setup time is 10 ns, requiring a maximum bus frequency of 50 MHz.
Values are measured from the TTL signal level (0.8 or 2.0 V) relative to the REFCLK rising edge.
SIU inputs are for the normal configuration (SIUBCR[EXDD] = 0—which gives an extra cycle for address inputs. When
SIUBCR[EXDD] = 1, address setup time is 10 ns, requiring a maximum bus frequency of 50 MHz.
2.6.4.1 Core Data Transfers
Generally, all MSC8102 bus and system output signals are driven from the rising edge of the reference
clock (REFCLK). The REFCLK is either the
Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and
T3 at the falling edge), as Figure 2-2 shows.
Figure 2-2 is a graphical representation of the internal ticks.
The UPM machine and GPCM machine outputs change on the internal tick determined by the memory
controller
change only on the
Table 2-11. AC Timing for SIU Inputs in Non-Pipelined Mode
Figure 2-2. Internal Tick Spacing for Memory Controller Signals
programming,
Table 2-12. AC Timing for SIU Inputs in Pipelined Mode
REFCLK
REFCLK
T1
the AC specifications are relative to the internal tick. SDRAM machine outputs
rising edge.
Characteristic
Characteristic
T2
DLLIN
T3
signal or, if DLL is disabled, the
T4
CLKOUT
Value Units
Value Units
4.5
5.5
0.5
4.5
0.5
3.5
3
5
3
5
6
6
4
4
signal.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns