MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 101

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
5 - 4
3 - 2
1 - 0
Bit
7
6
RxSTAT2 - 1
TxSTAT2-1
RQ9, RQ8
Idle Chan
INTGEN
Name
Interrupt Generated. Set to 1 when an interrupt (in conjunction with the Interrupt
Mask Register) has been generated by the HDLC. This is an asynchronous event.
It is reset when the interrupt Register is read.
Idle Channel. Set to a 1 when an idle Channel state (15 or more ones) has been
detected at the receiver. This is an asynchronous event. On power reset, this may
be 1 if the clock (RXC) was not operating. Status becomes valid after the first 15
bits or the first zero is received.
Byte Status bits from RX FIFO. These bits determine the status of the byte to be
read from RX FIFO as follows:
These bits determine the status of the TX FIFO as follows:
These bits determine the status of the RX FIFO as follows:
RxSTAT2 RxSTAT1 RX FIFO Status
TxSTAT2 TxSTAT1 TX FIFO Status
RQ9 RQ8 Byte Status
0
0
1
1
0
0
1
1
0
0
1
1
Table 145 - HDLC Status Register
0
1
0
1
0
1
0
1
Packet Byte
First Byte
Last byte of a good packet.
Last byte of a bad packet.
0
1
0
1
(Page B & C Address 14H)
TX FIFO full up to the selected status level or more.
The number of bytes in the TX FIFO has reached or
TX FIFO empty.
The number of bytes in the TX FIFO is less than the
selected interrupt threshold level.
exceeded the selected interrupt threshold level.
RX FIFO empty
The number of bytes in the RX FIFO is less
than the interrupt threshold level.
RX FIFO full.
The number of bytes in the RX FIFO has reached or
exceeded the interrupt threshold level.
Functional Description
MT9074
101