MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 99

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
Table 140 - HDLC Address Recognition Register
7 - 1 ADR26-20 Address 26 - 20. A seven bit
7 - 2 ADR16-11 Address 16 - 11. A six bit
Bit
Bit
0
1
0
Table 141 - HDLC Address Recognition
Register2 (Page B & C, Address 11H)
Name
ADR10
A2EN
Name
A1EN
(Page B & C, Address 10H)
address used for comparison with
the second byte of the received
address. ADR26 is MSB. This
mask is ignored (as well as first
byte mask) if all call address
(1111111) is received.
Second
Enable. When this bit is set high,
the above seven bit address is
used in the comparison of the
second address byte.
If address recognition is enabled,
any packet failing the address
comparison will not be stored in
the RX FIFO. A2EN must be high
for All-call address recognition.
When this bit is low, this bit mask
is ignored in address comparison
address used for comparison
with the first byte of the received
address. ADR16 is MSB.
Address 10. This bit is used in
address comparison if a seven
bit address is being checked for
(control bit four of control register
2 is set).
First
Enable. When this bit is high, the
above six (or seven) bit address
is used in the comparison of the
first address byte.
If address recognition is enabled,
any packet failing the address
comparison will not be stored in
the RX FIFO. A1EN must be high
for All-call (1111111) address
recognition
address. When this bit is low, this
bit mask is ignored in address
comparison
Functional Description
Functional Description
1
Address
Address
for
single
Comparison
Comparison
byte
7 - 0 BIT7-0 This eight bit word is tagged with the
7 - 0 BIT7-0 This is the received data byte read
Bit
Bit
Name
Name
Table 143 - RX FIFO Read Register
Table 142 - TX FIFO Write Register
(Page B & C, Address 12H)
(Page B & C, Address 12H)
two status bits from the control register
1 (EOP and FA), and the resulting 10
bit word is written to the TX FIFO. The
FIFO
immediately after a write or read
occurs. It is updated after the data has
settled and the transfer to the last
available position has finished.
from the RX FIFO. The status bits of
this byte can be read from the status
register. The FIFO status is not
changed immediately when a write or
read occurs. It is updated after the
data has settled and the transfer to the
last available position has finished.
Functional Description
Functional Description
status
is
not
MT9074
changed
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