MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 29

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
system the receive data is in phase with the E1.5o
clock, the C4b clock is phase-locked to the E1.5o
clock, and the read and write positions of the slip
buffer will remain fixed with respect to each other.
In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the PCM 30 signals from the network
are synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the E1.5o
clocks of non-synchronizer trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus.
Network standards state that, within limits, trunk
interfaces must be able to receive error-free data in
the presence of jitter and wander (refer to network
requirements for jitter and wander tolerance). The
MT9074 will allow a maximum of 26 channels (208
UI, unit intervals) of wander and low frequency jitter
before a frame slip will occur.
Write Vectors
188 uS
Read Vectors
Minimum Delay
Read Vectors - Maximum Delay
Read Pointer
Read Pointer
synchronizer,
249 uS
157 uS
512 Bit
Elastic
Store
Figure 13 - Read and write pointers in the receive slip buffers
Pointer
Read Pointer
Write
0 uS
Frame 0
which
32 uS
Frame 0
124 uS
Read Pointer
will
62 uS
XXX
function
Frame 1
Frame 1
as
92 uS
92 uS
The minimum delay through the receive slip buffer is
approximately two channels and the maximum delay
is approximately 60 channels (see Figure 14).
When the C4b and the E1.5o clocks are not phase-
locked, the rate at which data is being written into the
slip buffer from the PCM 30 side may differ from the
rate at which it is being read out onto the ST-BUS. If
this situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full PCM 30 frame is either repeated or lost. All
frame slips occur on PCM 30 frame boundaries.
Two status bits, RSLIP and RSLPD (page03H,
address13H) give indication of a slip occurrence and
direction. RSLIP changes state in the event of a slip.
If RSLPD=0, the slip buffer has overflowed and a
frame was lost; if RSLPD=1, an underflow condition
occurred and a frame was repeated. A maskable
interrupt SLPI (page 01H, address 1BH) is also
provided.
Figure 14 illustrates the relationship between the
read and write pointers of the receive slip buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the write
pointer a frame slip will occur, which will put the read
pointer
Conversely, if the read pointer moves more than 60
XXX
Frame 0
34
channels
XXX
from
Wander Tolerance
Frame 1
the
write
MT9074
XXX
pointer.
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