MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 50

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9074
50
7-5
Bit
4
3
2
1
0
Table 35 - Interrupt Mask Word Three (T1)
1SECIM
5SECIM
BIOMIM
LCDIM
SIGIM
Name
- - -
(Page 1, Address 1EH)
Unused.
Loop Code Detected Interrupt
Mask.
interrupt is triggered when either
the loop up (00001) or loop down
(001) code has been detected on
the line for a period of 48
milliseconds. If 1 - unmasked, 0 -
masked.
One Second Status Interrupt
Mask.
interrupt is initiated when the
1SEC status bit (page 3 address
12H bit 7) goes from low to high.
If 1 - unmasked, 0 - masked.
Five Second Status Interrupt
Mask.
interrupt is initiated when the 5
SEC status bit goes from low to
high. If 1 - unmasked, 0 -
masked.
Bit
Interrupt
unmasked an interrupt is initiated
when
111111110xxxxxx0
received on the FDL that is
different from the last message.
The new message must persist
for 8 out the last 10 message
positions to be accepted as a
valid
unmasked, 0 - masked.
Signalling
When unmasked an interrupt will
be initiated when a change of
state (optionally debounced - see
DBEn in the Data Link, Signalling
Control Word page 1 address
12H) is detected in the signalling
bits (AB or ABCD) pattern. If 1 -
unmasked, 0 - masked.
Functional Description
new
Oriented
When
When
When
Interrupt
message.
Mask.
a
unmasked
unmasked
unmasked
has
Message
pattern
Mask.
If
When
been
an
an
an
1-
2-0
Bit
6 -
7
4
3
RES2-0
REDBL
TXL2-0
Name
Table 36 - LIU Control Word (T1)
NRZ
(Page 1, Address 1FH)
NRZ Format Selection. Only
used in the digital framer only
mode (LIU is disabled). A one sets
the MT9074 to accept a unipolar
NRZ format input stream on RxA
as the line input, and to transmit a
unipolar NRZ format stream on
TxB. A zero causes the MT9074 to
accept a complementary pair of
dual rail inputs on RxA/RxB and to
transmit a complementary pair of
dual rail outputs on TxA/TxB.
Transmit Line Build Out 2 - 0.
Setting these bits shapes the
transmit pulse as detailed in the
table below:
TX22 TXL1 TXL0 Line Build Out
After reset these bits are zero.
Receive Equalizer Disable. If one
the receive equalizer is turned off.
If zero, the receive equalizer is
turned on and will compensate for
loop length automatically.
Receive
Setting these pins forces a level of
equalization of the incoming line
data.
RES2
Equalization
These settings have no effect if
REDBL is set to zero.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Functional Description
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Advance Information
RES1
0
Equalization
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 to 133 feet/ 0 dB
133 to 266 feet
266 to 399 feet
399 to 533 feet
533 to 655 feet
-7.5 dB
-15 dB
-22.5 dB
none
6dB
12dB
18dB
24dB
reserved
reserved
reserved
RES0
Receive
Select.
o