MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 92

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9074
92
Bit
7
6
5
4
3
2
1
0
PRBSMFO Pseudo Random Bit Sequence
FERRO
PRBSO
FEBEO
CRCO
Name
BPVO
Table 128 - Interrupt Word Two
- - -
- - -
(Page 4, Address 1DH) (E1)
Errored
Signal
Interrupt. When unmasked this
interrupt bit goes high whenever
the errored frame alignment signal
counter changes from FFH to 00H.
Reading this register clears this
bit.
CRC Error Counter Overflow
Interrupt. When unmasked this
interrupt bit goes high whenever
the CRC error counter changes
from FFH to 00H. Reading this
register clears this bit.
E-bit
Interrupt. When unmasked this
interrupt bit goes high whenever
the E-bit counter changes from
FFH to 00H. Reading this register
clears this bit.
Unused
Bipolar
Overflow
unmasked this interrupt bit goes
high whenever the bipolar violation
counter changes from FFH to 00H.
Reading this register clears this
bit.
Pseudo Random Bit Sequence
Error
Interrupt. When unmasked this
interrupt bit goes high whenever
the PRBS error counter changes
from FFH to 00H. Reading this
register clears this bit.
Multiframe
Interrupt. When unmasked this
interrupt bit goes high whenever
the multiframe counter attached to
the PRBS error counter overflows.
FFH to 00H. 1 - unmasked, 0 -
masked.
Unused
Functional Description
Counter
Counter
Framing
Counter
Violation
Counter
Interrupt.
Alignment
Overflow
Overflow
Overflow
Overflow
Counter
When
Bit
7
6
5
4
3
2
1
0
HDLC0I HDLC0
HDLC1I HDLC1
1SECI
5SECI
Name
RCRI
SIGI
- - -
JAI
Table 129 - Interrupt Word Three
(Page 4, Address 1EH) (E1)
Unused
unmasked HDLC0 interrupt occurs.
This bit goes high. Reading this
register clears this bit.
unmasked HDLC1 interrupt occurs.
this bit goes high. Reading this
register clears this bit.
Jitter Attenuator Error Interrupt.
Whenever an unmasked JAI interrupt
occurs.
If jitter attenuator FIFO comes within
four bytes of an overflow or underflow,
this bit goes high. Reading this
register clears this bit.
One Second Status Interrupt. When
unmasked this interrupt bit goes high
whenever the 1SEC status bit (page 3
address 12H bit 7) goes from low to
high. Reading this register clears this
bit.
Five Second Status Interrupt. When
unmasked this interrupt bit goes high
whenever the 5 SEC status bit goes
from low to high. Reading this register
clears this bit.
RCRI
unmasked RCRI interrupt occurs. If
remote alarm and CRC error occur
this bit goes high. Reading this
register clears this bit.
Signalling
unmasked this interrupt bit goes high
whenever
(optionally debounced - see DBEn in
the Data Link, Signalling Control
Word) is detected in the signalling bits
(AB or ABCD) pattern. Reading this
register clears this bit.
Functional Description
Interrupt.
Advance Information
Interrupt.
Interrupt.
a
Interrupt.
change
Whenever
Whenever
Whenever
of
When
state
an
an
an