MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 52

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9074
52
6-5
3-2
Bit
7
4
1
0
Table 38 - Configuration Control Word
ADSEQ
LIUEn
Name
T1/E1
RSV
RSV
RSV
(Page 2, Address 10H) (T1)
T1/E1 mode selection. when this
bit is zero, the device is in T1
mode. When set high, the device
is in E1 mode.
Reserved. Must be kept at 0 for
normal operation.
LIU Enable. Setting this bit low
enables the internal LIU front-end.
Setting this pin high disables the
LIU. Digital inputs RXA and RXB
are sampled by the rising edge of
E1.5i (C1.50) to strobe in the
received line data. Digital transmit
data is clocked out of pins TXA
and TXB with the rising edge of
C1.5o
Reserved. Must be kept at 0 for
normal operation.
Digital Milliwatt or Digital Test
Sequence. If one, the Alaw digital
milliwatt analog test sequence will
be selected for those channels
with per time slot control bits
TTST, RRST set. If zero, a PRBS
generator
connected to channels with TTST,
RRST respectively.
Reserved. Must be kept at 0 for
normal operation.
Functional Description
/
detector
will
be
6-4
2-0
6-0 CP6-0 Custom Pulse. These bits provide the
Bit
Bit
7
3
7
Name
Name
RSV
RSV
RSV
RSV
CPL
Table 39 - Custom Tx Pulse Enable
Table 40 - Custom Pulse Word 1
(Page 2, Address 1CH) (T1)
(Page 2, Address 11H) (T1)
Reserved. Must be kept high for
normal operation.
Reserved. Must be kept low for normal
operation.
Custom Pulse Level. Setting this bit
low enables the internal ROM values in
generating the transmit pulses. The
ROM is coded for different line
terminations or build out, as specified
in the LIU Control word. Setting this bit
high disables the pre-programmed
pulse templates. Each of the 4 phases
that generate a mark derive their D/A
coefficients
programmed in the CPW registers.
Reserved. Must be kept at 0 for normal
operation.
Reserved. Must be kept low for normal
operation.
capability
magnitude setting for the TTIP/TRING
line driver A/D converter during the first
phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.
Functional Description
Functional Description
Advance Information
for
from
programming
the
values
the