MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 68

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9074
Per Channel Receive Signalling (T1 and E1 mode) (Pages 9 and 0AH)
Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive
Signalling Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 76 illustrates the mapping
between the addresses of these pages and the DS1 channel numbers. Table 77 describes bit allocation within
each of these registers.
68
Page 9 Address:
Equivalent DS1
channel
Page A Address:
Equivalent DS1
channel
7 - 4
Bit
3
3
2
0
Table 77 - Receive Channel Associated Signalling (Pages 9 and A) (T1)
Name
A(n)
B(n)
C(n)
D(n)
- - -
Table 76 - Page 9, A Address Mapping to DS1 Channels (T1)
0
1
0
17
Unused
Receive Signalling Bits A for Channel n. These bits are extracted from bit
position 8 of every channel in received frame 6 (within the 12 frame superframe
structure for D4 superframes and the 24 frame structure for ESF superframes). The
bits may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.
Receive Signalling Bits B for Channel n. These bits are extracted from bit
position 8 of every channel in received frame 12 (within the 12 frame superframe
structure for D4 superframes and the 24 frame structure for ESF superframes). The
bits may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.
Receive Signalling Bits C for Channel n. These bits are extracted from bit
position 8 of every channel in received frame 18 within the 24 frame structure for
ESF superframes. The bits reported may be debounced for 6 to 9 milliseconds
where control bit DBNCE is set high. In D4 mode these bits are unused.
Receive Signalling Bits D for Channel n. These bits are extracted from bit
position 8 of every channel in received frame 24 within the 24 frame structure for
ESF superframes. The bits reported may be debounced for 6 to 9 milliseconds
where control bit DBNCE is set high. In D4 mode these bits are unused.
1
2
1
18
2
3
2
19
3
4
3
20
4
5
4
21
5
6
5
22
Functional Description
6
7
6
23
7
8
7
24
8
9
8
x
9
10
9
x
10
11
10
x
Advance Information
11
12
11
x
12
13
12
x
13
14
13
x
14
15
14
x
15
16
15
x