MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 43

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
4 - 3
Bit
7
6
5
Table 21 - Framing Mode Select (T1)
RS1- 0
SLC96
Name
CXC
ESF
(Page 1, Address 10H)
Extended
Setting
transmission and reception of
the 24 frame superframe DS1
protocol.
SLC96 Mode Select. Setting
this bit enables input and output
of the Fs bit pattern on the TxDL
and
synchronization is the same as
in the case of D4 operation. The
transmitter will insert A and B
bits
synchronizing to the Fs pattern
clocked into Txdl. Receive Fs
bits are not monitored for the
Framing Bit Error Counter.
Cross Check. Setting this bit in
ESF mode enables a cross
check of the CRC-6 remainder
before the frame synchronizer
pulls into sync. This process
adds at least 6 milliseconds to
the frame synchronization time.
Setting this bit in D4 (not ESF)
mode enables a check of the Fs
bits in addition to the Ft bits
during frame synchronization
Reframe Select 1 - 0. These
bits set the criteria for an
automatic reframe in the event
of framing bits errors. The
combinations available are:
RS1 - 0, RS0 - 0 = sliding
window of 2 errors out of 4.
RS1 - 0, RS0 - 1 = sliding
window of 2 errors out of 5.
RS1 - 1, RS0 - 0 = sliding
window of 2 errors out of 6.
RS1 - 1, RS0 - 1 = no reframes
due to framing bit errors.
Functional Description
every
RxDL
this
Super
6
pins.
bit
frames
enables
Frame.
Frame
after
Bit
2
1
0
Table 21 - Framing Mode Select (T1)
MFReFR
Name
ReFR
FSI
(Page 1, Address 10H)
Fs Bit Include. Only applicable
in D4 mode (not ESF or
SLC96). Setting this bit causes
errored Fs bits to be included as
framing bit errors. A bad Fs bit
will increment the Framing Error
Bit Counter, and will potentially
cause a reframe (if it is the
second bad framing bit out of 5).
The Fs bit of the receive frame
12 will only be included if
D4SECY is set low.
Reframe. Setting this bit causes
an automatic reframe.
MultiFrame
applicable in D4 or SLC96
mode. Setting this bit causes an
automatic multiframe reframe.
The signalling bits are frozen
until multiframe synchronization
is achieved. Terminal frame
synchronization is not affected.
Functional Description
Reframe.
MT9074
Only
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