MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 25

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
well as a receive to transmit loopback are also
supported. Transmit and receive bit rates and
enables can operate independently. In MT9074 the
transceiver can operate at a continuous rate
independent of RXcen and TXcen (free run mode) by
setting the Frun bit of Control Register 1.
Received packets from the serial interface are
sectioned into bytes by an HDLC receiver that
detects flags, checks for go-ahead signals, removes
inserted zeros, performs a cyclical redundancy
check (CRC) on incoming data, and monitors the
address if required. Packet reception begins upon
detection of an opening flag. The resulting bytes are
concatenated with two status bits (RQ9, RQ8) and
placed in a receiver first-in-first-out (Rx FIFO); a
buffer register that generates status and interrupts
for microprocessor read control.
In
microprocessor writes data bytes into a Tx buffer
register (Tx FIFO) that generates status and
interrupts. Packet transmission begins when the
microprocessor writes a byte to the Tx FIFO. Two
status bits are added to the Tx FIFO for transmitter
control of frame aborts (FA) and end of packet (EOP)
flags. Packets have flags appended, zeros inserted,
and a CRC, also referred to as frame checking
sequence (FCS), added automatically during serial
transmission. When the Tx FIFO is empty and
finished sending a packet, Interframe Time Fill bytes
(continuous flags (7E hex)), or Mark Idle (continuous
ones) are transmitted to indicate that the channel is
idle.
HDLC Transmitter
Following initialization and enabling, the transmitter
is in the Idle Channel state (Mark Idle), continuously
sending ones. Interframe Time Fill state (Flag Idle) is
selected by setting the Mark idle bit in Control
Register 1 high. The Transmitter remains in either of
these two states until data is written to the Tx FIFO.
Control Register 1 bits EOP (end of packet) and FA
(Frame Abort) are set as status bits before the
microprocessor loads 8 bits of data into the 10 bit
wide FIFO (8 bits data and 2 bits status). To change
the tag bits being loaded in the FIFO, Control
Register 1 must be written to before writing to the
FIFO. However, EOP and FA are reset after writing to
the TX FIFO. The Transmit Byte Count Register may
also be used to tag an end of packet. The register is
loaded with the number of bytes in the packet and
decrements after every write to the Tx FIFO. When a
count of one is reached, the next byte written to the
FIFO is tagged as an end of packet. The register
may be made to cycle through the same count if the
conjunction
with
the
control
circuitry,
the
packets are of the same length by setting Control
Register 2 bit Cycle.
If the transmitter is in the Idle Channel state when
data is written to the Tx FIFO, then an opening flag is
sent and data from Tx FIFO follows. Otherwise, data
bytes are transmitted as soon as the current flag byte
has been sent. Tx FIFO data bytes are continuously
transmitted until either the FIFO is empty or an EOP
or FA status bit is read by the transmitter. After the
last bit of the EOP byte has been transmitted, a 16-
bit FCS is sent followed by a closing flag. When
multiple packets of data are loaded into Tx FIFO,
only one flag is sent between packets.
Frame aborts (the transmission of 7F hex), are
transmitted by tagging a byte previously written to
the Tx FIFO. When a byte has an FA tag, then an FA
is sent instead of that tagged byte. That is, all bytes
previous to but not including that byte are sent. After
a Frame Abort, the transmitter returns to the Mark
Idle or Interframe Time Fill state, depending on the
state of the Mark idle control bit.
Tx FIFO underrun will occur if the FIFO empties and
the last byte did not have either an EOP or FA tag. A
frame abort sequence will be sent when an underrun
occurs.
Below is an example of the transmission of a three
byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill).
TXcen can be enabled before or after this sequence.
(a) Write ’04’hex to Control Register 1
(b) Write ’AA’ hex to TX FIFO
(c) Write ’03’hex to TX FIFO
(d) Write ’34’hex to Control Register 1
(e) Write ’77’hex to TX FIFO
The transmitter may be enabled independently of the
receiver. This is done by setting the TXEN bit of the
Control Register. Enabling happens immediately
upon writing to the register. Disabling using TXen will
occur after the completion of the transmission of the
present packet; the contents of the FIFO are not
cleared. Disabling will consist of stopping the
transmitter clock. The Status and Interrupt Registers
may still be read and the FIFO and Control Registers
may be written to while the transmitter is disabled.
The transmitted FCS may be inhibited using the Tcrci
bit of Control Register 2. In this mode the opening
-Mark idle bit set
-Data byte
-Data byte
-TXEN; EOP; Mark idle bits set
-Final data byte
MT9074
25