MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 46

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9074
46
Table 26 - Coding and Loopback Control Word
Bit
7
6
5
4
3
2
1
RxB8ZS
TxB8ZS
Name
MLBK
DLBK
RLBK
SLBK
FBS
(T1)(Page 1, Address 15H)
Receive B8ZS Enable. If one,
receive
enabled.
Metallic Loopback. If one, then
RRTIP/RRING
directly
respectively. If zero, this feature is
disabled. Set the transmit line
build out to -7.5dB when metallic
loopback is enabled.
Transmit B8ZS Enable. If one, all
zero octets are substituted with
B8ZS codes.
Forced Bit Stuffing. If set any
transmit DS0 channel containing
all zeros has bit 7 forced high.
Digital Loopback. If one, the
digital stream to the transmit LIU
is looped back in place of the
digital output of the receive LIU.
Data coming out of DSTo will be a
delayed version of DSTi. If zero,
this feature is disabled.
Remote Loopback. If one, all
time slots received on RRTIP/
RRING are connected to TTIP/
TRING on the DS1 side of the
MT9074. If zero, this feature is
disabled.
ST-BUS Loopback. If one, all
time slots of DSTi are connected
to DSTo on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. See Loopbacks section.
Functional Description
to
B8ZS
TTIP
are
decoding
and
connected
TRING
is
Table 26 - Coding and Loopback Control Word
7-0
7-0
Bit
Bit
Bit
0
Table 28 - Transmit Elastic Buffer Set Delay
Name
TxSD7-0 Transmit Set Delay Bits 7-0.
Name
- - -
Name
PLBK
Word (T1) (Page 1, Address 17H)
(T1)(Page 1, Address 15H)
Table 27 - Reserved (T1)
Unused
(Page 1, Address 16H)
Writing to this register forces a one
time setting of the delay through the
transmit slip buffer. Delay is defined
as the time interval between the
write of the transmit STBUS channel
containing DS1 timeslot 1 and its
subsequent read. Delay is modified
by moving the position of the
internally generated DS1 frame
boundary.Delay
always be less than 1 frame
(125uS). This register must be
programmed with a non-zero value
(such as 0FH).
Payload Loopback. If one, all
time slots received on RTIP/
RRING are connected to TTIP/
TRING on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. If receive robbed bit
signaling data is to be included in
the looped data, then the control
bit RBEn (Page 1 Address 14H,
Bit 5) must be set low, otherwise
transmit signaling data will be
placed into the LSB of each
timeslot every sixth frame. Setting
all Clear Channel control bits high
(Bit 0 in the Per Time Slot Control
words - Pages 7 and 8 Address
10H to IFH inclusive) has the
same effect as setting control bit
RBEn low.
Functional Description
Functional Description
Functional Description
Advance Information
(when
set)
will