PM7312 pmc-sierra, PM7312 Datasheet - Page 114

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Register 0x06C: DLL Vernier Control
The Vernier Control Register provides the delay line tap control when using the vernier option.
VERNIER[7:0]
The vernier tap register bits (VERNIER[7:0]) specifies the phase delay through the DLL when
using the vernier feature. When VERN_EN is set high, the VERNIER[7:0] registers specify the
delay tap used. When VERN_EN is set low, the VERNIER[7:0] register is ignored.
A VERNIER[7:0] value of all zeros specifies the delay tap with the minimum delay through the
delay line. A VERNIER[7:0] value of 255 specifies the delay tap with the maximum delay
through the delay line.
Bit
Bit 31
To
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
VERNIER[7]
VERNIER[6]
VERNIER[5]
VERNIER[4]
VERNIER[3]
VERNIER[2]
VERNIER[1]
VERNIER[0]
Default
X
0
0
0
0
0
0
0
0
Released
114