PM7312 pmc-sierra, PM7312 Datasheet - Page 52

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
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10.1 Interfaces
10.1.1
10.1.2
Functional Description
Scaleable Bandwidth Interconnect (SBI) Interface
The Scaleable Bandwidth Interconnect is a synchronous, time-division multiplexed bus designed to
transfer, in a pin-efficient manner, data belonging to a number of independently timed links of
varying bandwidth. The SBI interface supported in FREEDM 32A1024L is a parallel 8 bit
wide19.44 MHz or 77.76 MHz bus.
Timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures.
Payload indicator signals in the SBI control the position of the floating data structure and therefore
the timing. When sources are running faster than the SBI the floating payload structure is advanced
by an octet by passing an extra octet in the V3 octet locations. When the source is slower than the
SBI the floating payload is retarded by leaving the octet after the V3 octet unused. Both these rate
adjustments are indicated by the SBI control signals.
The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH
virtual tributary structure is used to carry T1/J1 and E1 links.
An SBI interface consists of a DROP BUS and an ADD BUS. On the DROP BUS all timing is
sourced from the PHY and is passed onto the FREEDM 32A1024L by the arrival rate of data over
the SBI. On the ADD BUS either the PHY or the FREEDM 32A1024L can control timing. When
the FREEDM 32A1024L is the timing master, the PHY device determines it’s transmit timing
information from the arrival rate of data across the SBI. When the PHY device is the timing master,
it signals the FREEDM 32A1024L to speed up or slow down with justification request signals. The
PHY timing master indicates a speedup request to the Link Layer by asserting the justification
request signal high during the V3 octet of the DROP bus. When this is detected by the FREEDM
32A1024L it will advance the channel by inserting data in the next V3 octet as described above.
The PHY timing master indicates a slowdown request to the FREEDM 32A1024L by asserting the
justification request signal high during the octet after the V3 octet of the DROP bus. The FREEDM
32A1024L responds by leaving the octet following the next V3 octet unused. Both advance and
retard rate adjustments take place in the frame or multi-frame following the justification request.
The SBI structure uses a locked SONET/SDH structure fixing the position of the TUG-3/TU-3
relative to the STS-12/STM-4 transport frame. The SBI is also of fixed frequency and alignment as
determined by the reference clock (REFCLK) and frame indicator signal (AC1FP or DC1FP).
Adjusting the location of the T1/J1/E1 channels using floating tributaries as determined by the V5
indicator and payload signals (DV5, AV5, DPL and APL) compensates frequency deviations.
The multiplexed links are separated into three Synchronous Payload Envelopes. Each envelope
may be configured independently to carry up to 28 T1/J1s or 21 E1s.
Any-PHY Interface
The Any-PHY Interface is an asynchronous interface that supports the transfer of data to and from
the Any-PHY channels within the FREEDM 32A1024L. Two variants of the Any-PHY interface are
supported in FREEDM 32A1024L: a parallel 52 MHz 16 bit wide bus (Any-PHY Level 2), and a
parallel 8 bit wide 104 MHz bus (Any-PHY Level-3).
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
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