PM7312 pmc-sierra, PM7312 Datasheet - Page 62

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
10.4 Loop Back
10.4.1
10.4.2
10.5 Initialization Process
fragmentation size is referenced to the number of bytes transferred on the link and includes the
multi-link header.
On an HDLC channel and priority basis the datagrams are decomposed into chunks and are stored
in an external SDRAM memory. A chunk is defined as a fixed length unit of data (32 bytes) plus a 4
byte header, or a partially completed unit of data. A chunk will only consist of data from one
packet/frame.
The Egress Queue Manager maintains a separate linked list of chunks for each HDLC channel and
priority level. Single link HDLC channels have two priority levels whereas HDLC channels, which
are part of multi-link bundles, have only one priority level.
The chunk transmitter controls a 64 Kbyte partial packet RAM. A data chunk is transferred from
external memory into the partial packet RAM in a burst. Data is read from the RAM a byte at a time
and delivered to the HDLC engine. The chunk transmitter can support 1024 simultaneous byte
transfer sessions (one per HDLC channel). As chunks are depleted, the chunk transmitter requests
the next chunk for the associated HDLC channel from the egress queue manager. The egress queue
manager will read a chunk from the appropriate link list, giving preference to high priority data
over low priority data.
The HDLC engine receives the incoming byte stream and encapsulates the data stream with a
HDLC header, bit stuffing and a FCS trailer. The HDLC engine is capable of simultaneously
processing 1024 independent HDLC channels. The resulting HDLC data and status is passed to the
de-channelizer to be transferred onto the links.
Data arriving at the SBI interface is inserted into the SBI format at the correct tributary and timeslot
associated with a HDLC channel.
SBI Line Loop Back
When enabled, the data on tributary #n output by the EXSBI block is looped back to the tributary
#n in the INSBI block. (Note: The FREEDM must be the master of the tributary to enable SBI line
loop back.)
When loop back is disabled, transmit data for tributary #n is provided by the TCAS-12 block (i.e.
processed normally).
System Side Loop Back
The loop back controller block in the RCAS-12 TSB implements the channel based diagnostic loop
back function. Every valid data byte belonging to a channel with diagnostic loop back enabled
from the Transmit HDLC Processor / Partial Packet Buffer block (THDL-12) is written into a 1024
word FIFO in the RCAS-12 block. The loop back controller monitors for an idle time-slot or a
time-slot carrying a channel with diagnostic loop back enabled. If either condition holds, the
current data byte is replaced by data retrieved from the loop back data FIFO.
Configuration of a channel/CI cannot be changed while data is flowing on that channel/CI.
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
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