PM7312 pmc-sierra, PM7312 Datasheet - Page 37

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Pin Name
RXDATA[0]
RXDATA[1]
RXDATA[2]
RXDATA[3]
RXDATA[4]
RXDATA[5]
RXDATA[6]
RXDATA[7]
RXDATA[8]
RXDATA[9]
RXDATA[10]
RXDATA[11]
RXDATA[12]
RXDATA[13]
RXDATA[14]
RXDATA[15]
RXPRTY
Type
Tristate
Output
Tristate
Output
Pin No.
AD3
AD2
AC5
AD1
AC4
AC2
AB5
AC1
AB4
AB3
AB2
AB1
AA4
AA3
AA2
Y5
Y4
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Any-PHY Level 2 Mode
The receive data signals (RXDATA[15:0]) contain the receive Any-
PHY packet interface (APPI) data output by the FREEDM
32A1024L when selected. Data is presented in big endian format;
i.e. the byte in RXDATA[15:8] was received by the FREEDM
32A1024L before the byte in RXDATA[7:0].
The first word of each data transfer (when RSX is high) contains an
address to identify the device and Any-PHY channel associated
with the data being transferred. The second and any subsequent
words of each data transfer contain valid data. The FREEDM
32A1024L may be programmed to overwrite RXDATA[7:0] of the
final word of each packet transfer (REOP is high) with the status of
packet reception when that packet is erred (RERR is high). This
status information is encoded as follows:
RXDATA[7:0]
Note 1: Excessive Number of Fragments only applies when the
output format is frame/packet out (not fragment out).
Note 2: Sequenced Datagram Treated as Non-sequenced occurs
when the DONT_RESEQ or DO_NOT_RESEQ bits are used.
The RXDATA[15:0] signals are tristated when the FREEDM
32A1024L device is not selected via the RENB signal.
The RXDATA[15:0] signals are updated on the rising edge of
RXCLK.
Any-PHY Level 3 Mode:
The receive data signals (RXDATA[7:0]) contain the receive Any-
PHY packet interface (APPI) data output by the FREEDM
32A1024L when selected.
The first and second bytes of each data transfer contains an
address to identify the device and channel associated with the data
being transferred. The third and any subsequent bytes of each data
transfer contain valid data. The FREEDM 32A1024L may be
programmed to overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP is high) with the status of packet reception
when that packet is erred (RERR is high). This status information is
encoded as for the Any-PHY Level 2 Mode (above).
The RXDATA[15:8] signals are tristated when the FREEDM
32A1024L device operating in 8 bit mode.
The RXDATA[7:0] signals are driven but not considered valid when
the RENB signal is high.
The RXDATA[7:0] signals are updated on the rising edge of
RXCLK.
Any-PHY Level 2 Mode
The receive parity signal (RXPRTY) reflects the odd parity
01H
02H
04H
08H
10H
81H
82H
84H
88H
90H
A0H
Error
Channel FIFO Overrun
Packet Length violation
FCS Error
Non-Octet Aligned
HDLC Packet Abort
Unexpected Presence of SN
Unsupported Header Format
Lost Datagram
Unexpected SN
Excessive Number of Fragments
Seq. Datagram Treated as Non-seq.
Released
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