PM7312 pmc-sierra, PM7312 Datasheet - Page 40

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Pin Name
Table 4 Re-Sequencing SDRAM Interface (52 Signals)
Pin Name
RSCSB
RSRASB
RSCASB
RSWEB
RSADD[0]
RSADD[1]
RSADD[2]
RSADD[3]
RSADD[4]
RSADD[5]
RSADD[6]
RSADD[7]
RSADD[8]
RSADD[9]
RSADD[10]
RSADD[11]
RSADD[12]
RSBS[0]
RSBS[1]
RSDAT[0]
RSDAT[1]
RSDAT[2]
RSDAT[3]
RSDAT[4]
RSDAT[5]
RSDAT[6]
RSDAT[7]
RSDAT[8]
Type
Output
Output
Output
Output
Output
Output
I/O
Type
Pin No.
Pin No.
AB31
AB30
AB29
AA28
V28
V27
W31
W30
W29
W27
Y31
Y30
Y29
Y28
Y27
AA30
AA29
AB28
AC31
AB27
AC30
AC29
AC28
AD31
AC27
AD28
AE31
AD27
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Any-PHY Level 2 Mode:
RVAL is tristated when the FREEDM 32A1024L device is not
selected via the RENB signal.
Any-PHY Level 3 Mode:
RVAL is driven low when the FREEDM 32A1024L device is not
selected via the RENB signal.
Function
Re-Sequencing SDRAM Chip Select Bar. RSCSB, RSRASB,
RSCASB, and RSWEB define the command being sent to the
SDRAM.
RSCSB is updated on the rising edge of SYSCLK.
Re-Sequencing SDRAM Row Address Strobe Bar. RSCSB,
RSRASB, RSCASB, and RSWEB define the command being sent
to the SDRAM.
RSRASB is updated on the rising edge of SYSCLK.
Re-Sequencing SDRAM Column Address Strobe Bar. RSCSB,
RSRASB, RSCASB, and RSWEB define the command being sent
to the SDRAM.
RSCASB is updated on the rising edge of SYSCLK.
Re-Sequencing SDRAM Write Enable Bar. RSCSB, RSRASB,
RSCASB, and RSWEB define the command being sent to the
SDRAM.
RSWEB is updated on the rising edge of SYSCLK.
Re-Sequencing SDRAM Address. The Re-Sequencing SDRAM
address outputs identify the row address (RSADD[12:0]) and
column address (RSADD[8:0]) for the locations accessed.
RSADD[12:0] is updated on the rising edge of SYSCLK.
Re-Sequencing SDRAM Bank Select. The bank select signal
determines which bank of a dual/quad bank Re-Sequencing
SDRAM chip is active. RSBS[1:0] is generated along with the row
address when RSRASB is asserted low.
RSBS is updated on the rising edge of SYSCLK.
Re-Sequencing SDRAM Data. The bi-directional Re-Sequencing
SDRAM data bus pins interface directly with the Re-Sequencing
SDRAM data ports.
RSDAT[31:0] is updated/tristated on the rising edge of SYSCLK.
Released
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