PM7312 pmc-sierra, PM7312 Datasheet - Page 6

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
11 Normal Mode Register Description....................................................................................... 95
12 Test Features Description ................................................................................................... 247
13 Operation ............................................................................................................................ 249
14 Functional Timing................................................................................................................ 253
15 Absolute Maximum Ratings ................................................................................................ 267
16 Normal Operating Conditions ............................................................................................. 268
17 Power Information............................................................................................................... 269
18 D.C. Characteristics ............................................................................................................ 271
19 A.C. Timing Characteristics ................................................................................................ 272
10.4 Loop Back ................................................................................................................... 62
10.5 Initialization Process ................................................................................................... 62
10.6 Any-PHY Tear Down Procedure.................................................................................. 63
10.7 CI Tear Down Procedure............................................................................................. 64
10.8 Restrictions on Any-PHY to CI Mapping ..................................................................... 64
10.9 Block Descriptions....................................................................................................... 65
11.1 Microprocessor Accessible Registers ......................................................................... 95
11.2 Microprocessor Accessible Memories....................................................................... 227
12.1 Test Mode Registers ................................................................................................. 247
12.2 JTAG Test Port .......................................................................................................... 247
13.1 JTAG Support............................................................................................................ 249
14.1 SBI Drop Bus Interface Timing.................................................................................. 253
14.2 SBI Add Bus Interface Timing ................................................................................... 253
14.3 Receive APPI Timing (Any-PHY Level 2).................................................................. 254
14.4 Transmit APPI Timing (Any-PHY Level 2)................................................................. 257
14.5 Receive APPI Timing (Any-PHY Level 3).................................................................. 259
14.6 Transmit APPI Timing (Any-PHY Level 3)................................................................. 260
14.7 Re-Sequencing SDRAM Interface ............................................................................ 262
14.8 Chunk Buffer SDRAM Interface ................................................................................ 263
14.9 Context SSRAM Interface (ZBT SSRAM mode)....................................................... 263
14.10 Microprocessor Interface .......................................................................................... 264
17.1 Power Requirements................................................................................................. 269
17.2 Power Sequencing .................................................................................................... 269
17.3 Power Supply Filtering .............................................................................................. 270
19.1 SBI Bus Interface Timing .......................................................................................... 272
19.2 SBI Add Bus Interface Timing ................................................................................... 273
19.3 Any-PHY Timing........................................................................................................ 275
19.4 Microprocessor Timing .............................................................................................. 277
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
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