PM7312 pmc-sierra, PM7312 Datasheet - Page 265

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Figure 56 Read and Write to Non-burstable Register Space
Figure 57 shows a burst read and write operation (only valid for burstable registers) with bus
polarity set to 0. The first and third accesses illustrate transfers that are terminated by the FREEDM
32A1024L via the assertion of BTERMB. The second and fourth accesses illustrate transfers that
are terminated by the external interface via the assertion of BLAST. Note that between each
transfer, there is no turn around cycle. Care must be taken to examine the AC timing to ensure that
there is no bus contention on the AD bus between a read followed by a write transfer. BTERMB is
only asserted when the burst access is 4 cycles long. It is not asserted if the burst cycle is terminated
by BLAST or for non-burst accesses (BURSTB=1).
Figure 57 Read and Write to Burstable Address Space
BTERMB
READYB
BUSPOL
AD(31:0)
BURSTB
BLAST
ADSB
BCLK
CSB
WR
BTERMB
BUSPOL
BURSTB
READYB
AD(31:0)
BLAST
ADSB
BCLK
CSB
WR
1
1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536
2
Read, 3 wait cycles
Read, 3 wait cycles
A
3
A
4
D
5
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
6
Burst read, 3 wait cycles, mbtermb used
Burst read, 3 wait cycles, mbtermb used
A
7
D
8
D
9
Write, 1 wait cycle
Write, 1 wait cycle
A
10
Burst read, 4 wait cycles, no mbtermb
Burst read, 4 wait cycles, no mbtermb
A
11
D
D
12
13
Burst write, 1 wait cycle, mbterm
Burst write, 1 wait cycle, mbterm
A
14
A
15
Read, 4 wait cycles
Read, 4 wait cycles
D
16
D
Burst read, 3
Burst read, 3
17
A
18
D
Released
19
D
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